Refactor rx_lo_init
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parent
25c1e608e3
commit
2693c18fdc
30
src/main.c
30
src/main.c
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@ -59,8 +59,8 @@ static int gains[NUM_GAINS] = { 0, 9, 14, 27, 37, 77, 87, 125, 144, 157
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static int gain = INIT_GAIN;
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static int sample_rate = INIT_SAMPLE_RATE;
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#define SIN_PHASE (UINT_MAX / 4)
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#define COS_PHASE (0)
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#define SIN_PHASE (0u)
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#define COS_PHASE (3u << 30)
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/* rx -> cp -> cos -> sin -> pio_cos -> pio_sin -> rx ... */
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static int dma_ch_rx = -1;
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@ -236,33 +236,35 @@ static void adder_init()
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pio_sm_set_enabled(pio1, 3, true);
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}
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static void lo_generate(uint32_t *buf, size_t len, double freq, unsigned phase)
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static void lo_generate(uint32_t *buf, double freq, uint32_t phase)
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{
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static const double base = (UINT_MAX + 1.0) / CLK_SYS_HZ;
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unsigned step = base * freq;
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unsigned accum = phase;
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uint32_t step = base * freq;
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for (size_t i = 0; i < len; i++) {
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for (size_t i = 0; i < LO_WORDS; i++) {
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unsigned bits = 0;
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for (int j = 0; j < 32; j++) {
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bits |= accum >> 31;
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bits |= phase >> 31;
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bits <<= 1;
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accum += step;
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phase += step;
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}
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buf[i] = bits;
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}
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}
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static void rx_lo_init(double req_freq)
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static void rx_lo_init(double req_freq, bool align)
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{
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const double step_hz = (double)CLK_SYS_HZ / (4 << LO_BITS_DEPTH);
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double freq = round(req_freq / step_hz) * step_hz;
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double freq = req_freq;
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lo_generate(lo_cos, LO_WORDS, freq, COS_PHASE);
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lo_generate(lo_sin, LO_WORDS, freq, SIN_PHASE);
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if (align)
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freq = round(freq / step_hz) * step_hz;
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lo_generate(lo_cos, freq, COS_PHASE);
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lo_generate(lo_sin, freq, SIN_PHASE);
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}
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static const uint32_t samp_insn[4] __attribute__((__aligned__(16)));
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@ -571,7 +573,7 @@ static void run_command(uint8_t cmd, uint32_t arg)
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{
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if (0x01 == cmd) {
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/* Tune to a new center frequency */
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rx_lo_init(arg);
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rx_lo_init(arg, true);
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} else if (0x02 == cmd) {
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/* Set the rate at which IQ sample pairs are sent */
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sample_rate = arg;
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@ -699,7 +701,7 @@ int main()
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queue_init(&iq_queue, sizeof(uint8_t *), IQ_QUEUE_LEN);
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rx_lo_init(INIT_FREQ);
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rx_lo_init(INIT_FREQ, true);
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while (true) {
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if (check_command() > 0) {
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