mordae/pico-sdr
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Drop speed to 240 MHz

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This commit is contained in:
Jan Hamal Dvořák 2025-08-31 13:59:17 +02:00
parent e38ddd5961
commit 45bcde411c
Signed by: mordae
GPG key ID: 1782BCC23EE007B9
2 changed files with 18 additions and 15 deletions
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11
src/CMakeLists.txt
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@ -36,5 +36,16 @@ target_compile_definitions(pico_sdr PUBLIC PICO_STDIO_DEFAULT_CRLF=0)
target_include_directories(pico_sdr PRIVATE include) target_include_directories(pico_sdr PRIVATE include)
target_compile_definitions(pico_sdr PRIVATE
PLL_SYS_REFDIV=1
PLL_SYS_VCO_FREQ_HZ=2400000000
PLL_SYS_POSTDIV1=5
PLL_SYS_POSTDIV2=2
SYS_CLK_HZ=240000000
SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST=1
SYS_CLK_VREG_VOLTAGE_MIN=VREG_VOLTAGE_1_30
)
#pico_set_binary_type(pico_sdr no_flash) #pico_set_binary_type(pico_sdr no_flash)
pico_set_binary_type(pico_sdr copy_to_ram) pico_set_binary_type(pico_sdr copy_to_ram)

22
src/main.c
View file

@ -21,9 +21,6 @@
#include <limits.h> #include <limits.h>
#include <stdlib.h> #include <stdlib.h>
#define VREG_VOLTAGE VREG_VOLTAGE_1_30
#define CLK_SYS_HZ (300 * MHZ)
#define RX_PIN 10 #define RX_PIN 10
#define FB_PIN 6 #define FB_PIN 6
#define PSU_PIN 23 #define PSU_PIN 23
@ -59,7 +56,7 @@ static int sample_rate = INIT_SAMPLE_RATE;
#define BASE_GAIN (1 << 23) #define BASE_GAIN (1 << 23)
#define DC_OFFSET (int)(127.4 * (1 << ATTN_BITS)) #define DC_OFFSET (int)(127.4 * (1 << ATTN_BITS))
static int gain = BASE_GAIN / (CLK_SYS_HZ / INIT_SAMPLE_RATE); static int gain = BASE_GAIN / (SYS_CLK_HZ / INIT_SAMPLE_RATE);
static queue_t iq_queue; static queue_t iq_queue;
static uint8_t iq_queue_buffer[IQ_QUEUE_LEN][IQ_BLOCK_LEN]; static uint8_t iq_queue_buffer[IQ_QUEUE_LEN][IQ_BLOCK_LEN];
@ -241,9 +238,9 @@ static void lo_generate_phase(uint32_t *buf, size_t len, uint32_t step, uint32_t
static void rx_lo_init(double freq) static void rx_lo_init(double freq)
{ {
double n = round(freq * (8 << LO_BITS_DEPTH) / CLK_SYS_HZ); double n = round(freq * (8 << LO_BITS_DEPTH) / SYS_CLK_HZ);
freq = n * CLK_SYS_HZ / (8 << LO_BITS_DEPTH); freq = n * SYS_CLK_HZ / (8 << LO_BITS_DEPTH);
uint32_t step = freq * 4294967296.0 / CLK_SYS_HZ; uint32_t step = freq * 4294967296.0 / SYS_CLK_HZ;
lo_generate_phase(lo_cos, LO_WORDS, step, COS_PHASE); lo_generate_phase(lo_cos, LO_WORDS, step, COS_PHASE);
lo_generate_phase(lo_sin, LO_WORDS, step, SIN_PHASE); lo_generate_phase(lo_sin, LO_WORDS, step, SIN_PHASE);
} }
@ -512,8 +509,8 @@ static void run_command(uint8_t cmd, uint32_t arg)
} else if (0x02 == cmd) { } else if (0x02 == cmd) {
/* Set the rate at which IQ sample pairs are sent */ /* Set the rate at which IQ sample pairs are sent */
sample_rate = arg; sample_rate = arg;
gain = BASE_GAIN / (CLK_SYS_HZ / sample_rate); gain = BASE_GAIN / (SYS_CLK_HZ / sample_rate);
dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / sample_rate); dma_timer_set_fraction(dma_t_samp, 1, SYS_CLK_HZ / sample_rate);
rx_lo_init(frequency); rx_lo_init(frequency);
} }
} }
@ -580,11 +577,6 @@ done:
int main() int main()
{ {
vreg_set_voltage(VREG_VOLTAGE);
set_sys_clock_khz(CLK_SYS_HZ / KHZ, true);
clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, CLK_SYS_HZ,
CLK_SYS_HZ);
/* Enable PSU PWM mode. */ /* Enable PSU PWM mode. */
gpio_init(PSU_PIN); gpio_init(PSU_PIN);
gpio_set_dir(PSU_PIN, GPIO_OUT); gpio_set_dir(PSU_PIN, GPIO_OUT);
@ -606,7 +598,7 @@ int main()
/* We need to have the sampling timer ready. */ /* We need to have the sampling timer ready. */
dma_t_samp = dma_claim_unused_timer(true); dma_t_samp = dma_claim_unused_timer(true);
dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / sample_rate); dma_timer_set_fraction(dma_t_samp, 1, SYS_CLK_HZ / sample_rate);
while (true) { while (true) {
if (check_command() > 0) { if (check_command() > 0) {