Update 40.68 MHz settings

This commit is contained in:
Jan Hamal Dvořák 2024-03-17 16:06:15 +01:00
parent d8395922da
commit 9519be4e76
2 changed files with 15 additions and 14 deletions

View file

@ -77,18 +77,19 @@ blocks:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [712, 496.0]
coordinate: [704, 496.0]
rotation: 0
state: true
- name: blocks_interleaved_char_to_complex_0
id: blocks_interleaved_char_to_complex
- name: blocks_interleaved_short_to_complex_0
id: blocks_interleaved_short_to_complex
parameters:
affinity: ''
alias: ''
comment: ''
maxoutbuf: '0'
minoutbuf: '0'
scale_factor: '127'
scale_factor: (1 << 15) - 1
swap: 'False'
vector_input: 'False'
states:
bus_sink: false
@ -172,7 +173,7 @@ blocks:
minoutbuf: '0'
port: '1234'
server: 'True'
type: byte
type: short
vlen: '1'
states:
bus_sink: false
@ -598,7 +599,7 @@ blocks:
grid: 'True'
gui_hint: (0, 0, 1, 2)
int_max: '0'
int_min: '-90'
int_min: 10 * math.log10(1 / ((2 ** 15 - 1) ** 2))
label1: ''
label10: ''
label2: ''
@ -628,15 +629,15 @@ blocks:
connections:
- [analog_quadrature_demod_cf_0, '0', qtgui_time_sink_x_0_0, '0']
- [blocks_interleaved_char_to_complex_0, '0', analog_quadrature_demod_cf_0, '0']
- [blocks_interleaved_char_to_complex_0, '0', blocks_probe_rate_0, '0']
- [blocks_interleaved_char_to_complex_0, '0', digital_costas_loop_cc_0, '0']
- [blocks_interleaved_char_to_complex_0, '0', qtgui_time_sink_x_0, '0']
- [blocks_interleaved_char_to_complex_0, '0', qtgui_waterfall_sink_x_0_0, '0']
- [blocks_interleaved_short_to_complex_0, '0', analog_quadrature_demod_cf_0, '0']
- [blocks_interleaved_short_to_complex_0, '0', blocks_probe_rate_0, '0']
- [blocks_interleaved_short_to_complex_0, '0', digital_costas_loop_cc_0, '0']
- [blocks_interleaved_short_to_complex_0, '0', qtgui_time_sink_x_0, '0']
- [blocks_interleaved_short_to_complex_0, '0', qtgui_waterfall_sink_x_0_0, '0']
- [blocks_probe_rate_0, rate, blocks_message_debug_0, print]
- [digital_costas_loop_cc_0, '0', qtgui_const_sink_x_0, '0']
- [digital_costas_loop_cc_0, '0', qtgui_time_sink_x_0_1, '0']
- [network_tcp_source_0, '0', blocks_interleaved_char_to_complex_0, '0']
- [network_tcp_source_0, '0', blocks_interleaved_short_to_complex_0, '0']
metadata:
file_format: 1

View file

@ -54,9 +54,9 @@
#define CLK_SYS_HZ (250 * MHZ)
#define BANDWIDTH 1280000
#define DECIMATION_BITS 6
#define LPF_ORDER 3
#define LPF_ORDER 4
#define AGC_DECAY_BITS 16
#define BIAS_STRENGTH 5
#define BIAS_STRENGTH 3
#endif
#define IQ_BLOCK_LEN 32