mordae/pico-sdr
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Swap SM constant names

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This commit is contained in:
Jan Hamal Dvořák 2024-08-03 00:10:12 +02:00
parent 82c1c12195
commit f866c97fcb
1 changed files with 29 additions and 29 deletions
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58
src/main.c
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@ -30,10 +30,10 @@
#define PSU_PIN 23 #define PSU_PIN 23
#define PIO pio1 #define PIO pio1
#define LO_SM 0 #define SM_LO 0
#define FB_SM 1 #define SM_FB 1
#define RX_SM 2 #define SM_RX 2
#define AD_SM 3 #define SM_AD 3
#define IQ_SAMPLES 32 #define IQ_SAMPLES 32
#define IQ_BLOCK_LEN (2 * IQ_SAMPLES) #define IQ_BLOCK_LEN (2 * IQ_SAMPLES)
@ -130,8 +130,8 @@ static void init_lo()
.origin = origin_lo, .origin = origin_lo,
}; };
pio_sm_restart(PIO, LO_SM); pio_sm_restart(PIO, SM_LO);
pio_sm_clear_fifos(PIO, LO_SM); pio_sm_clear_fifos(PIO, SM_LO);
if (pio_can_add_program(PIO, &prog)) if (pio_can_add_program(PIO, &prog))
origin_lo = pio_add_program(PIO, &prog); origin_lo = pio_add_program(PIO, &prog);
@ -143,10 +143,10 @@ static void init_lo()
sm_config_set_clkdiv_int_frac(&pc, 1, 0); sm_config_set_clkdiv_int_frac(&pc, 1, 0);
sm_config_set_fifo_join(&pc, PIO_FIFO_JOIN_TX); sm_config_set_fifo_join(&pc, PIO_FIFO_JOIN_TX);
sm_config_set_out_shift(&pc, false, true, 32); sm_config_set_out_shift(&pc, false, true, 32);
pio_sm_init(PIO, LO_SM, origin_lo, &pc); pio_sm_init(PIO, SM_LO, origin_lo, &pc);
pio_sm_set_consecutive_pindirs(PIO, LO_SM, LO_PIN, 1, GPIO_IN); pio_sm_set_consecutive_pindirs(PIO, SM_LO, LO_PIN, 1, GPIO_IN);
pio_sm_exec_wait_blocking(PIO, LO_SM, pio_encode_set(pio_pins, 0)); pio_sm_exec_wait_blocking(PIO, SM_LO, pio_encode_set(pio_pins, 0));
} }
static void init_fb() static void init_fb()
@ -173,8 +173,8 @@ static void init_fb()
.origin = origin_fb, .origin = origin_fb,
}; };
pio_sm_restart(PIO, FB_SM); pio_sm_restart(PIO, SM_FB);
pio_sm_clear_fifos(PIO, FB_SM); pio_sm_clear_fifos(PIO, SM_FB);
if (pio_can_add_program(PIO, &prog)) if (pio_can_add_program(PIO, &prog))
origin_fb = pio_add_program(PIO, &prog); origin_fb = pio_add_program(PIO, &prog);
@ -187,9 +187,9 @@ static void init_fb()
sm_config_set_sideset_pins(&pc, FB_PIN); sm_config_set_sideset_pins(&pc, FB_PIN);
sm_config_set_wrap(&pc, origin_fb, origin_fb + prog.length - 1); sm_config_set_wrap(&pc, origin_fb, origin_fb + prog.length - 1);
sm_config_set_clkdiv_int_frac(&pc, 1, 0); sm_config_set_clkdiv_int_frac(&pc, 1, 0);
pio_sm_init(PIO, FB_SM, origin_fb, &pc); pio_sm_init(PIO, SM_FB, origin_fb, &pc);
pio_sm_set_consecutive_pindirs(PIO, FB_SM, FB_PIN, 1, GPIO_OUT); pio_sm_set_consecutive_pindirs(PIO, SM_FB, FB_PIN, 1, GPIO_OUT);
} }
static void init_rx() static void init_rx()
@ -207,8 +207,8 @@ static void init_rx()
.origin = origin_rx, .origin = origin_rx,
}; };
pio_sm_restart(PIO, RX_SM); pio_sm_restart(PIO, SM_RX);
pio_sm_clear_fifos(PIO, RX_SM); pio_sm_clear_fifos(PIO, SM_RX);
if (pio_can_add_program(PIO, &prog)) if (pio_can_add_program(PIO, &prog))
origin_rx = pio_add_program(PIO, &prog); origin_rx = pio_add_program(PIO, &prog);
@ -219,9 +219,9 @@ static void init_rx()
sm_config_set_clkdiv_int_frac(&pc, 1, 0); sm_config_set_clkdiv_int_frac(&pc, 1, 0);
sm_config_set_fifo_join(&pc, PIO_FIFO_JOIN_RX); sm_config_set_fifo_join(&pc, PIO_FIFO_JOIN_RX);
sm_config_set_in_shift(&pc, false, true, 32); sm_config_set_in_shift(&pc, false, true, 32);
pio_sm_init(PIO, RX_SM, origin_rx, &pc); pio_sm_init(PIO, SM_RX, origin_rx, &pc);
pio_sm_set_consecutive_pindirs(PIO, RX_SM, RX_PIN, 1, GPIO_IN); pio_sm_set_consecutive_pindirs(PIO, SM_RX, RX_PIN, 1, GPIO_IN);
} }
static void init_ad() static void init_ad()
@ -263,8 +263,8 @@ static void init_ad()
.origin = origin_ad, .origin = origin_ad,
}; };
pio_sm_restart(PIO, AD_SM); pio_sm_restart(PIO, SM_AD);
pio_sm_clear_fifos(PIO, AD_SM); pio_sm_clear_fifos(PIO, SM_AD);
if (pio_can_add_program(PIO, &prog)) if (pio_can_add_program(PIO, &prog))
pio_add_program(PIO, &prog); pio_add_program(PIO, &prog);
@ -274,7 +274,7 @@ static void init_ad()
sm_config_set_clkdiv_int_frac(&pc, 1, 0); sm_config_set_clkdiv_int_frac(&pc, 1, 0);
sm_config_set_in_shift(&pc, false, true, 32); sm_config_set_in_shift(&pc, false, true, 32);
sm_config_set_out_shift(&pc, false, true, 32); sm_config_set_out_shift(&pc, false, true, 32);
pio_sm_init(PIO, AD_SM, origin_ad, &pc); pio_sm_init(PIO, SM_AD, origin_ad, &pc);
} }
#define STEP_BASE ((UINT_MAX + 1.0) / CLK_SYS_HZ) #define STEP_BASE ((UINT_MAX + 1.0) / CLK_SYS_HZ)
@ -335,18 +335,18 @@ static void rf_rx_start()
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32); channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
channel_config_set_read_increment(&dma_conf, false); channel_config_set_read_increment(&dma_conf, false);
channel_config_set_write_increment(&dma_conf, false); channel_config_set_write_increment(&dma_conf, false);
channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, RX_SM, GPIO_IN)); channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_RX, GPIO_IN));
channel_config_set_chain_to(&dma_conf, dma_ch_rx2); channel_config_set_chain_to(&dma_conf, dma_ch_rx2);
dma_channel_configure(dma_ch_rx1, &dma_conf, &PIO->txf[AD_SM], &PIO->rxf[RX_SM], UINT_MAX, dma_channel_configure(dma_ch_rx1, &dma_conf, &PIO->txf[SM_AD], &PIO->rxf[SM_RX], UINT_MAX,
false); false);
dma_conf = dma_channel_get_default_config(dma_ch_rx2); dma_conf = dma_channel_get_default_config(dma_ch_rx2);
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32); channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
channel_config_set_read_increment(&dma_conf, false); channel_config_set_read_increment(&dma_conf, false);
channel_config_set_write_increment(&dma_conf, false); channel_config_set_write_increment(&dma_conf, false);
channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, RX_SM, GPIO_IN)); channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_RX, GPIO_IN));
channel_config_set_chain_to(&dma_conf, dma_ch_rx1); channel_config_set_chain_to(&dma_conf, dma_ch_rx1);
dma_channel_configure(dma_ch_rx2, &dma_conf, &PIO->txf[AD_SM], &PIO->rxf[RX_SM], UINT_MAX, dma_channel_configure(dma_ch_rx2, &dma_conf, &PIO->txf[SM_AD], &PIO->rxf[SM_RX], UINT_MAX,
false); false);
/* Drive the LO capacitor. */ /* Drive the LO capacitor. */
@ -362,9 +362,9 @@ static void rf_rx_start()
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32); channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
channel_config_set_read_increment(&dma_conf, true); channel_config_set_read_increment(&dma_conf, true);
channel_config_set_write_increment(&dma_conf, false); channel_config_set_write_increment(&dma_conf, false);
channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, LO_SM, GPIO_OUT)); channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_LO, GPIO_OUT));
channel_config_set_chain_to(&dma_conf, dma_ch_mix1); channel_config_set_chain_to(&dma_conf, dma_ch_mix1);
dma_channel_configure(dma_ch_mix2, &dma_conf, &PIO->txf[LO_SM], NULL, LO_PHASE_WORDS, dma_channel_configure(dma_ch_mix2, &dma_conf, &PIO->txf[SM_LO], NULL, LO_PHASE_WORDS,
false); false);
/* Trigger accumulator values push. */ /* Trigger accumulator values push. */
@ -374,7 +374,7 @@ static void rf_rx_start()
channel_config_set_write_increment(&dma_conf, false); channel_config_set_write_increment(&dma_conf, false);
channel_config_set_high_priority(&dma_conf, true); channel_config_set_high_priority(&dma_conf, true);
channel_config_set_dreq(&dma_conf, dma_get_timer_dreq(dma_t_samp)); channel_config_set_dreq(&dma_conf, dma_get_timer_dreq(dma_t_samp));
dma_channel_configure(dma_ch_samp_cos, &dma_conf, &PIO->sm[AD_SM].instr, &samp_insn, dma_channel_configure(dma_ch_samp_cos, &dma_conf, &PIO->sm[SM_AD].instr, &samp_insn,
UINT_MAX, false); UINT_MAX, false);
init_ad(); init_ad();
@ -630,8 +630,8 @@ static void do_rx()
channel_config_set_read_increment(&dma_conf, false); channel_config_set_read_increment(&dma_conf, false);
channel_config_set_write_increment(&dma_conf, true); channel_config_set_write_increment(&dma_conf, true);
channel_config_set_ring(&dma_conf, GPIO_OUT, RX_BITS_DEPTH); channel_config_set_ring(&dma_conf, GPIO_OUT, RX_BITS_DEPTH);
channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, AD_SM, false)); channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_AD, false));
dma_channel_configure(dma_ch_in_cos, &dma_conf, rx_cos, &PIO->rxf[AD_SM], UINT_MAX, true); dma_channel_configure(dma_ch_in_cos, &dma_conf, rx_cos, &PIO->rxf[SM_AD], UINT_MAX, true);
multicore_launch_core1(rf_rx); multicore_launch_core1(rf_rx);