mordae/pico-sdr
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mordae:superhet
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compare: mordae:45bcde411cbe1038abec9a05156fbc22f139f516
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mordae:superhet
mordae:old
mordae:qsd
mordae:superhet-amp
mordae:headphones

4 commits
fc7b24977c ... 45bcde411c

Author SHA1 Message Date
Jan Hamal Dvořák
45bcde411c
Drop speed to 240 MHz 2025-08-31 13:59:17 +02:00
Jan Hamal Dvořák
e38ddd5961
Use __aligned 2025-08-31 13:47:32 +02:00
Jan Hamal Dvořák
eb52048770
Improve frequency rounding 2025-08-30 21:44:29 +02:00
Jan Hamal Dvořák
4b9f377bb0
Fix DC offset removal, simplify... 2025-08-30 20:33:37 +02:00
2 changed files with 91 additions and 139 deletions
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11
src/CMakeLists.txt
View file

@ -36,5 +36,16 @@ target_compile_definitions(pico_sdr PUBLIC PICO_STDIO_DEFAULT_CRLF=0)
target_include_directories(pico_sdr PRIVATE include)
target_compile_definitions(pico_sdr PRIVATE
PLL_SYS_REFDIV=1
PLL_SYS_VCO_FREQ_HZ=2400000000
PLL_SYS_POSTDIV1=5
PLL_SYS_POSTDIV2=2
SYS_CLK_HZ=240000000
SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST=1
SYS_CLK_VREG_VOLTAGE_MIN=VREG_VOLTAGE_1_30
)
#pico_set_binary_type(pico_sdr no_flash)
pico_set_binary_type(pico_sdr copy_to_ram)

219
src/main.c
View file

@ -21,45 +21,42 @@
#include <limits.h>
#include <stdlib.h>
#define VREG_VOLTAGE VREG_VOLTAGE_1_20
#define CLK_SYS_HZ (320 * MHZ)
#define RX_PIN 10
#define FB_PIN 6
#define RX_PIN 10
#define FB_PIN 6
#define PSU_PIN 23
#define PIO pio0
#define SM_RX 0
#define PIO pio0
#define SM_RX 0
#define SM_BIAS 1
#define SM_COS 2
#define SM_SIN 3
#define SM_COS 2
#define SM_SIN 3
#define IQ_SAMPLES 32
#define IQ_SAMPLES 32
#define IQ_BLOCK_LEN (2 * IQ_SAMPLES)
#define IQ_QUEUE_LEN 16
#define XOR_ADDR 0x1000
#define LO_BITS_DEPTH 15
#define LO_WORDS (1 << (LO_BITS_DEPTH - 2))
#define XOR_ADDR 0x1000
#define LO_BITS_DEPTH 15
#define LO_WORDS (1 << (LO_BITS_DEPTH - 2))
#define LO_COS_ACCUMULATOR (&PIO->sm[SM_COS].pinctrl)
#define LO_SIN_ACCUMULATOR (&PIO->sm[SM_SIN].pinctrl)
#define SIN_PHASE (0u)
#define COS_PHASE (3u << 30)
#define SIN_PHASE (0u)
#define COS_PHASE (3u << 30)
static uint32_t lo_cos[LO_WORDS] __attribute__((__aligned__(1 << LO_BITS_DEPTH)));
static uint32_t lo_sin[LO_WORDS] __attribute__((__aligned__(1 << LO_BITS_DEPTH)));
static uint32_t lo_cos[LO_WORDS] __aligned(1 << LO_BITS_DEPTH);
static uint32_t lo_sin[LO_WORDS] __aligned(1 << LO_BITS_DEPTH);
#define INIT_SAMPLE_RATE 100000
#define INIT_FREQ 94600000
#define INIT_FREQ 94600000
static int frequency = INIT_FREQ;
static int sample_rate = INIT_SAMPLE_RATE;
#define BASE_GAIN (1 << 15)
#define ATTN_BITS 12
#define DECIMATE 4
#define ATTN_BITS 16
#define BASE_GAIN (1 << 23)
#define DC_OFFSET (int)(127.4 * (1 << ATTN_BITS))
static int gain = BASE_GAIN / (CLK_SYS_HZ / INIT_SAMPLE_RATE);
static int gain = BASE_GAIN / (SYS_CLK_HZ / INIT_SAMPLE_RATE);
static queue_t iq_queue;
static uint8_t iq_queue_buffer[IQ_QUEUE_LEN][IQ_BLOCK_LEN];
@ -108,7 +105,7 @@ static void init_rx()
pio_gpio_init(PIO, RX_PIN);
const uint16_t insn[] = {
pio_encode_in(pio_pins, 1) | pio_encode_delay(0),
pio_encode_in(pio_pins, 1),
};
pio_program_t prog = {
@ -143,16 +140,8 @@ static void init_bias()
gpio_set_slew_rate(FB_PIN, GPIO_SLEW_RATE_SLOW);
const uint16_t insn[] = {
pio_encode_mov(pio_isr, pio_null),
pio_encode_in(pio_y, 4),
pio_encode_in(pio_pins, 1) | pio_encode_delay(15),
pio_encode_in(pio_pins, 1) | pio_encode_delay(15),
pio_encode_mov(pio_y, pio_isr),
pio_encode_mov(pio_x, pio_isr),
pio_encode_jmp_x_dec(6),
pio_encode_mov_not(pio_pins, pio_pins) | pio_encode_sideset(1, 1),
pio_encode_mov_not(pio_pins, pio_pins) | pio_encode_sideset(1, 1) |
pio_encode_delay(0),
};
pio_program_t prog = {
@ -249,9 +238,9 @@ static void lo_generate_phase(uint32_t *buf, size_t len, uint32_t step, uint32_t
static void rx_lo_init(double freq)
{
double frac = (double)CLK_SYS_HZ / (8 << LO_BITS_DEPTH);
freq = roundf(freq / frac) * frac;
uint32_t step = freq * 4294967296.0 / CLK_SYS_HZ;
double n = round(freq * (8 << LO_BITS_DEPTH) / SYS_CLK_HZ);
freq = n * SYS_CLK_HZ / (8 << LO_BITS_DEPTH);
uint32_t step = freq * 4294967296.0 / SYS_CLK_HZ;
lo_generate_phase(lo_cos, LO_WORDS, step, COS_PHASE);
lo_generate_phase(lo_sin, LO_WORDS, step, SIN_PHASE);
}
@ -286,7 +275,7 @@ static void rf_rx_start()
channel_config_set_write_increment(&dma_conf, false);
channel_config_set_chain_to(&dma_conf, dma_ch_cos);
dma_channel_configure(dma_ch_cp, &dma_conf, LO_SIN_ACCUMULATOR, LO_COS_ACCUMULATOR, 1,
false);
false);
/* Read lo_cos into accumulator I with XOR. */
dma_conf = dma_channel_get_default_config(dma_ch_cos);
@ -296,7 +285,7 @@ static void rf_rx_start()
channel_config_set_ring(&dma_conf, false, LO_BITS_DEPTH);
channel_config_set_chain_to(&dma_conf, dma_ch_sin);
dma_channel_configure(dma_ch_cos, &dma_conf, LO_COS_ACCUMULATOR + XOR_ADDR / 4, lo_cos, 1,
false);
false);
/* Read lo_sin into accumulator Q with XOR. */
dma_conf = dma_channel_get_default_config(dma_ch_sin);
@ -306,7 +295,7 @@ static void rf_rx_start()
channel_config_set_ring(&dma_conf, false, LO_BITS_DEPTH);
channel_config_set_chain_to(&dma_conf, dma_ch_pio_cos);
dma_channel_configure(dma_ch_sin, &dma_conf, LO_SIN_ACCUMULATOR + XOR_ADDR / 4, lo_sin, 1,
false);
false);
/* Copy mixed I accumulator to PIO adder I. */
dma_conf = dma_channel_get_default_config(dma_ch_pio_cos);
@ -316,7 +305,7 @@ static void rf_rx_start()
channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_COS, true));
channel_config_set_chain_to(&dma_conf, dma_ch_pio_sin);
dma_channel_configure(dma_ch_pio_cos, &dma_conf, &PIO->txf[SM_COS], LO_COS_ACCUMULATOR, 1,
false);
false);
/* Copy mixed Q accumulator to PIO adder Q. */
dma_conf = dma_channel_get_default_config(dma_ch_pio_sin);
@ -326,7 +315,7 @@ static void rf_rx_start()
channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_SIN, true));
channel_config_set_chain_to(&dma_conf, dma_ch_rx);
dma_channel_configure(dma_ch_pio_sin, &dma_conf, &PIO->txf[SM_SIN], LO_SIN_ACCUMULATOR, 1,
false);
false);
/* Trigger I accumulator values push. */
dma_conf = dma_channel_get_default_config(dma_ch_samp_cos);
@ -337,7 +326,7 @@ static void rf_rx_start()
channel_config_set_high_priority(&dma_conf, true);
channel_config_set_chain_to(&dma_conf, dma_ch_samp_sin);
dma_channel_configure(dma_ch_samp_cos, &dma_conf, &PIO->sm[SM_COS].instr, &samp_insn, 1,
false);
false);
/* Trigger Q accumulator values push. */
dma_conf = dma_channel_get_default_config(dma_ch_samp_sin);
@ -347,7 +336,7 @@ static void rf_rx_start()
channel_config_set_high_priority(&dma_conf, true);
channel_config_set_chain_to(&dma_conf, dma_ch_samp_cos);
dma_channel_configure(dma_ch_samp_sin, &dma_conf, &PIO->sm[SM_SIN].instr, &samp_insn, 1,
false);
false);
init_bias();
init_adder();
@ -426,92 +415,50 @@ inline static void led_set(bool on)
gpio_put(PICO_DEFAULT_LED_PIN, on);
}
inline static uint32_t pio_sm_get_blocking_unsafe(pio_hw_t *pio, int sm)
{
while (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm)))
asm volatile("nop");
return pio->rxf[sm];
}
static int Ia1, Ia2, Ia3;
static int Ib1, Ib2, Ib3;
static int Qa1, Qa2, Qa3;
static int Qb1, Qb2, Qb3;
inline static void accI()
{
static uint16_t py, px;
uint32_t yx = pio_sm_get_blocking_unsafe(PIO, SM_COS);
uint16_t y = yx >> 16;
uint16_t x = yx;
uint16_t ny = py - y;
uint16_t nx = px - x;
py = y;
px = x;
uint32_t s = (ny << 1) + nx;
Ia1 += s;
Ia2 += Ia1;
Ia3 += Ia2;
}
inline static void accQ()
{
static uint16_t py, px;
uint32_t yx = pio_sm_get_blocking_unsafe(PIO, SM_SIN);
uint16_t y = yx >> 16;
uint16_t x = yx;
uint16_t ny = py - y;
uint16_t nx = px - x;
py = y;
px = x;
uint32_t s = (ny << 1) + nx;
Qa1 += s;
Qa2 += Qa1;
Qa3 += Qa2;
}
inline static int getI()
{
uint32_t c1, c2, c3;
static uint16_t py, px;
c3 = Ia3 - Ib3;
Ib3 = Ia3;
uint32_t yx = pio_sm_get_blocking(PIO, SM_COS);
uint16_t y = yx >> 16;
uint16_t x = yx;
c2 = c3 - Ib2;
Ib2 = c3;
uint16_t ny = py - y;
uint16_t nx = px - x;
c1 = c2 - Ib1;
Ib1 = c2;
py = y;
px = x;
return (int)c1;
int s = ((ny << 1) + nx) * gain;
static int dc;
dc += (s - dc) >> ATTN_BITS;
s -= dc;
return (s + DC_OFFSET) >> ATTN_BITS;
}
inline static int getQ()
{
uint32_t c1, c2, c3;
static uint16_t py, px;
c3 = Qa3 - Qb3;
Qb3 = Qa3;
uint32_t yx = pio_sm_get_blocking(PIO, SM_SIN);
uint16_t y = yx >> 16;
uint16_t x = yx;
c2 = c3 - Qb2;
Qb2 = c3;
uint16_t ny = py - y;
uint16_t nx = px - x;
c1 = c2 - Qb1;
Qb1 = c2;
py = y;
px = x;
return (int)c1;
int s = ((ny << 1) + nx) * gain;
static int dc;
dc += (s - dc) >> ATTN_BITS;
s -= dc;
return (s + DC_OFFSET) >> ATTN_BITS;
}
static void rf_rx(void)
@ -527,19 +474,21 @@ static void rf_rx(void)
uint8_t *blockptr = block;
for (int i = 0; i < IQ_SAMPLES; i++) {
for (int d = 0; d < DECIMATE; d++) {
accI();
accQ();
}
int I = getI();
int Q = getQ();
int I = getI() * gain;
int Q = getQ() * gain;
if (I < 0)
I = 0;
else if (I > 255)
I = 255;
I >>= ATTN_BITS;
*blockptr++ = I + 128;
if (Q < 0)
Q = 0;
else if (Q > 255)
Q = 255;
Q >>= ATTN_BITS;
*blockptr++ = Q + 128;
*blockptr++ = I;
*blockptr++ = Q;
}
if (queue_try_add(&iq_queue, &block)) {
@ -560,8 +509,8 @@ static void run_command(uint8_t cmd, uint32_t arg)
} else if (0x02 == cmd) {
/* Set the rate at which IQ sample pairs are sent */
sample_rate = arg;
gain = BASE_GAIN / (CLK_SYS_HZ / sample_rate);
dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / (sample_rate * DECIMATE));
gain = BASE_GAIN / (SYS_CLK_HZ / sample_rate);
dma_timer_set_fraction(dma_t_samp, 1, SYS_CLK_HZ / sample_rate);
rx_lo_init(frequency);
}
}
@ -613,10 +562,7 @@ static void do_rx()
fwrite(block, IQ_BLOCK_LEN, 1, stdout);
fflush(stdout);
} else {
int wait = xorshift() >> (32 - 15);
for (int i = 0; i < wait; i++)
asm volatile("nop");
sleep_us(10);
}
}
@ -631,11 +577,6 @@ done:
int main()
{
vreg_set_voltage(VREG_VOLTAGE);
set_sys_clock_khz(CLK_SYS_HZ / KHZ, true);
clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, CLK_SYS_HZ,
CLK_SYS_HZ);
/* Enable PSU PWM mode. */
gpio_init(PSU_PIN);
gpio_set_dir(PSU_PIN, GPIO_OUT);
@ -657,13 +598,13 @@ int main()
/* We need to have the sampling timer ready. */
dma_t_samp = dma_claim_unused_timer(true);
dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / (sample_rate * DECIMATE));
dma_timer_set_fraction(dma_t_samp, 1, SYS_CLK_HZ / sample_rate);
while (true) {
if (check_command() > 0) {
static const uint32_t header[3] = { __builtin_bswap32(0x52544c30),
__builtin_bswap32(5),
__builtin_bswap32(29) };
__builtin_bswap32(5),
__builtin_bswap32(29) };
fwrite(header, sizeof header, 1, stdout);
fflush(stdout);