Implement full-blown NCO using DMA sniffer
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src/main.c
140
src/main.c
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@ -24,6 +24,10 @@
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#define VREG_VOLTAGE VREG_VOLTAGE_1_20
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#define CLK_SYS_HZ (288 * MHZ)
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#define INIT_SAMPLE_RATE 100000
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#define INIT_FREQ 94600000
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#define INIT_GAIN 127
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#define LO_PIN 9
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#define RX_PIN 13
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#define FB_PIN 5
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@ -39,19 +43,23 @@
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#define IQ_BLOCK_LEN (2 * IQ_SAMPLES)
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#define IQ_QUEUE_LEN 8
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#define LO_NUM_PHASES (1 << 6)
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#define LO_PHASE_BITS 10
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#define LO_PHASE_WORDS (1 << (LO_PHASE_BITS - 2))
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#define LO_COS_PHASES (1 << 14)
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#define LO_EFFECTIVE_BITS (32 * LO_PHASE_WORDS * LO_COS_PHASES)
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/*
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* NOTE: Must have 256 phases with 256 bytes each.
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* Otherwise the DMA 1-byte write trick wouldn't work.
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*/
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const double step_hz = (double)CLK_SYS_HZ / (LO_EFFECTIVE_BITS / 2.0);
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#define LO_NUM_PHASES 256
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#define LO_PHASE_BITS 8
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#define LO_PHASE_WORDS (1 << (LO_PHASE_BITS - 2))
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#define STEP_BASE ((UINT_MAX + 1.0) / CLK_SYS_HZ)
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static uint32_t nco_step = (uint32_t)(STEP_BASE * INIT_FREQ) * 32 * LO_PHASE_WORDS;
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static uint32_t nco_null = 0;
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static uint32_t lo_phase[LO_NUM_PHASES][LO_PHASE_WORDS]
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__attribute__((__aligned__(LO_NUM_PHASES * 4 * LO_PHASE_WORDS)));
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static const uint32_t *lo_cos_phases[LO_COS_PHASES]
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__attribute__((__aligned__(1 << LO_PHASE_BITS)));
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static uint32_t nco_addr = (uint32_t)lo_phase;
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#define DECIMATE 16
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#define RX_BITS_DEPTH 10
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@ -62,10 +70,6 @@ static uint32_t rx_cos[RX_WORDS] __attribute__((__aligned__(1 << RX_BITS_DEPTH))
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static const uint32_t *rx_start = rx_cos;
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static const uint32_t *rx_end = rx_cos + RX_WORDS - 1;
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#define INIT_SAMPLE_RATE 100000
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#define INIT_FREQ 94600000
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#define INIT_GAIN 127
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#define NUM_GAINS 29
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static int gains[NUM_GAINS] = { 0, 9, 14, 27, 37, 77, 87, 125, 144, 157,
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166, 197, 207, 229, 254, 280, 297, 328, 338, 364,
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@ -78,8 +82,10 @@ static int frequency = INIT_FREQ;
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static int dma_ch_rx1 = -1;
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static int dma_ch_rx2 = -1;
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static int dma_ch_mix1 = -1;
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static int dma_ch_mix2 = -1;
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static int dma_ch_nco1 = -1;
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static int dma_ch_nco2 = -1;
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static int dma_ch_nco3 = -1;
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static int dma_ch_mix = -1;
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static int dma_ch_samp_cos = -1;
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@ -224,6 +230,8 @@ static void init_rx()
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pio_sm_set_consecutive_pindirs(PIO, SM_RX, RX_PIN, 1, GPIO_IN);
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}
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static const uint32_t samp_insn = 16;
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static void init_ad()
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{
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const uint16_t insn[] = {
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@ -277,8 +285,6 @@ static void init_ad()
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pio_sm_init(PIO, SM_AD, origin_ad, &pc);
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}
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#define STEP_BASE ((UINT_MAX + 1.0) / CLK_SYS_HZ)
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static void lo_generate_phase(uint32_t *buf, size_t len, uint32_t step, uint32_t phase)
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{
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for (size_t i = 0; i < len; i++) {
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@ -294,37 +300,25 @@ static void lo_generate_phase(uint32_t *buf, size_t len, uint32_t step, uint32_t
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}
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}
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static void rx_lo_init(double req_freq, bool align)
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static void rx_lo_init(double freq)
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{
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double freq = req_freq;
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if (align)
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freq = round(freq / step_hz) * step_hz;
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uint32_t step = STEP_BASE * freq;
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for (uint32_t i = 0; i < LO_NUM_PHASES; i++)
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lo_generate_phase(lo_phase[i], LO_PHASE_WORDS, step,
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i << (__builtin_clz(LO_NUM_PHASES) + 1));
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lo_generate_phase(lo_phase[i], LO_PHASE_WORDS, step, i << 24);
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uint32_t phase_step = step * 32 * LO_PHASE_WORDS;
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uint32_t phase = 0;
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for (uint32_t i = 0; i < LO_COS_PHASES; i++) {
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lo_cos_phases[i] = lo_phase[phase >> (__builtin_clz(LO_NUM_PHASES) + 1)];
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phase += phase_step;
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}
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nco_step = step * 32 * LO_PHASE_WORDS;
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}
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static const uint32_t samp_insn = 16;
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static void rf_rx_start()
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{
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dma_ch_rx1 = dma_claim_unused_channel(true);
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dma_ch_rx2 = dma_claim_unused_channel(true);
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dma_ch_mix1 = dma_claim_unused_channel(true);
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dma_ch_mix2 = dma_claim_unused_channel(true);
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dma_ch_nco1 = dma_claim_unused_channel(true);
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dma_ch_nco2 = dma_claim_unused_channel(true);
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dma_ch_nco3 = dma_claim_unused_channel(true);
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dma_ch_mix = dma_claim_unused_channel(true);
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dma_ch_samp_cos = dma_claim_unused_channel(true);
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@ -349,22 +343,42 @@ static void rf_rx_start()
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dma_channel_configure(dma_ch_rx2, &dma_conf, &PIO->txf[SM_AD], &PIO->rxf[SM_RX], UINT_MAX,
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false);
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/* Drive the LO capacitor. */
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dma_conf = dma_channel_get_default_config(dma_ch_mix1);
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/* Step the NCO. */
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dma_conf = dma_channel_get_default_config(dma_ch_nco1);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, true);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_ring(&dma_conf, GPIO_IN, LO_PHASE_BITS);
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dma_channel_configure(dma_ch_mix1, &dma_conf, &dma_hw->ch[dma_ch_mix2].al3_read_addr_trig,
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lo_cos_phases, 1, false);
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channel_config_set_chain_to(&dma_conf, dma_ch_nco2);
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dma_channel_configure(dma_ch_nco1, &dma_conf, &nco_null, &nco_step, 1, false);
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dma_conf = dma_channel_get_default_config(dma_ch_mix2);
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/* DMA above will increment the phase accumulator. */
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dma_sniffer_enable(dma_ch_nco1, DMA_SNIFF_CTRL_CALC_VALUE_SUM, true);
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/* Prepare the phase address. */
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dma_conf = dma_channel_get_default_config(dma_ch_nco2);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_8);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_chain_to(&dma_conf, dma_ch_nco3);
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dma_channel_configure(dma_ch_nco2, &dma_conf, (uint8_t *)(&nco_addr) + 1,
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((uint8_t *)&dma_hw->sniff_data) + 3, 1, false);
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/* Trigger LO using the address. */
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dma_conf = dma_channel_get_default_config(dma_ch_nco3);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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dma_channel_configure(dma_ch_nco3, &dma_conf, &dma_hw->ch[dma_ch_mix].al3_read_addr_trig,
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&nco_addr, 1, false);
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/* Drive the LO capacitor. */
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dma_conf = dma_channel_get_default_config(dma_ch_mix);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, true);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_LO, GPIO_OUT));
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channel_config_set_chain_to(&dma_conf, dma_ch_mix1);
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dma_channel_configure(dma_ch_mix2, &dma_conf, &PIO->txf[SM_LO], NULL, LO_PHASE_WORDS,
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channel_config_set_chain_to(&dma_conf, dma_ch_nco1);
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dma_channel_configure(dma_ch_mix, &dma_conf, &PIO->txf[SM_LO], lo_phase, LO_PHASE_WORDS,
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false);
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/* Trigger accumulator values push. */
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@ -383,7 +397,7 @@ static void rf_rx_start()
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init_rx();
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dma_channel_start(dma_ch_rx1);
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dma_channel_start(dma_ch_mix1);
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dma_channel_start(dma_ch_nco1);
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dma_channel_start(dma_ch_samp_cos);
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pio_set_sm_mask_enabled(PIO, 0x0f, true);
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@ -397,32 +411,42 @@ static void rf_rx_stop(void)
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dma_channel_clear_chain_to(dma_ch_rx1);
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dma_channel_clear_chain_to(dma_ch_rx2);
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dma_channel_clear_chain_to(dma_ch_mix1);
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dma_channel_clear_chain_to(dma_ch_mix2);
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dma_channel_clear_chain_to(dma_ch_nco1);
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dma_channel_clear_chain_to(dma_ch_nco2);
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dma_channel_clear_chain_to(dma_ch_nco3);
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dma_channel_clear_chain_to(dma_ch_mix);
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dma_channel_clear_chain_to(dma_ch_samp_cos);
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dma_channel_abort(dma_ch_rx1);
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dma_channel_abort(dma_ch_rx2);
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dma_channel_abort(dma_ch_mix1);
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dma_channel_abort(dma_ch_mix2);
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dma_channel_abort(dma_ch_nco1);
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dma_channel_abort(dma_ch_nco2);
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dma_channel_abort(dma_ch_nco3);
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dma_channel_abort(dma_ch_mix);
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dma_channel_abort(dma_ch_samp_cos);
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dma_channel_cleanup(dma_ch_rx1);
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dma_channel_cleanup(dma_ch_rx2);
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dma_channel_cleanup(dma_ch_mix1);
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dma_channel_cleanup(dma_ch_mix2);
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dma_channel_cleanup(dma_ch_nco1);
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dma_channel_cleanup(dma_ch_nco2);
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dma_channel_cleanup(dma_ch_nco3);
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dma_channel_cleanup(dma_ch_mix);
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dma_channel_cleanup(dma_ch_samp_cos);
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dma_channel_unclaim(dma_ch_rx1);
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dma_channel_unclaim(dma_ch_rx2);
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dma_channel_unclaim(dma_ch_mix1);
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dma_channel_unclaim(dma_ch_mix2);
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dma_channel_unclaim(dma_ch_nco1);
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dma_channel_unclaim(dma_ch_nco2);
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dma_channel_unclaim(dma_ch_nco3);
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dma_channel_unclaim(dma_ch_mix);
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dma_channel_unclaim(dma_ch_samp_cos);
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dma_ch_rx1 = -1;
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dma_ch_rx2 = -1;
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dma_ch_mix1 = -1;
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dma_ch_mix2 = -1;
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dma_ch_nco1 = -1;
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dma_ch_nco2 = -1;
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dma_ch_nco3 = -1;
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dma_ch_mix = -1;
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dma_ch_samp_cos = -1;
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}
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@ -572,13 +596,13 @@ static void run_command(uint8_t cmd, uint32_t arg)
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if (0x01 == cmd) {
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/* Tune to a new center frequency */
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frequency = arg;
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rx_lo_init(frequency + sample_rate, true);
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rx_lo_init(frequency + sample_rate);
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} else if (0x02 == cmd) {
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/* Set the rate at which IQ sample pairs are sent */
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sample_rate = arg;
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dc_level = CLK_SYS_HZ / sample_rate / 2;
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dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / (sample_rate * DECIMATE));
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rx_lo_init(frequency + sample_rate, true);
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rx_lo_init(frequency + sample_rate);
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} else if (0x04 == cmd) {
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/* Set the tuner gain level */
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gain = INIT_GAIN * powf(10.0f, arg / 200.0f);
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@ -692,7 +716,7 @@ int main()
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queue_init(&iq_queue, sizeof(uint8_t *), IQ_QUEUE_LEN);
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rx_lo_init(frequency + sample_rate, true);
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rx_lo_init(frequency + sample_rate);
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dma_t_samp = dma_claim_unused_timer(true);
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dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / (sample_rate * DECIMATE));
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