737 lines
19 KiB
C
737 lines
19 KiB
C
#include <pico/stdlib.h>
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#include <pico/stdio_usb.h>
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#include <pico/multicore.h>
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#include <pico/util/queue.h>
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#include <hardware/clocks.h>
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#include <hardware/dma.h>
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#include <hardware/gpio.h>
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#include <hardware/pll.h>
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#include <hardware/vreg.h>
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#include <hardware/sync.h>
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#include <hardware/pio.h>
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#include <hardware/pwm.h>
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#include <hardware/interp.h>
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#include <hardware/regs/clocks.h>
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#include <hardware/structs/bus_ctrl.h>
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#include <math.h>
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#include <stdio.h>
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#include <limits.h>
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#include <stdlib.h>
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#define VREG_VOLTAGE VREG_VOLTAGE_1_20
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#define CLK_SYS_HZ (288 * MHZ)
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#define INIT_SAMPLE_RATE 100000
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#define INIT_FREQ 94600000
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#define INIT_GAIN 127
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#define LO_PIN 9
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#define RX_PIN 13
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#define FB_PIN 5
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#define PSU_PIN 23
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#define PIO pio1
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#define SM_LO 0
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#define SM_FB 1
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#define SM_RX 2
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#define SM_AD 3
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#define IQ_SAMPLES 32
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#define IQ_BLOCK_LEN (2 * IQ_SAMPLES)
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#define IQ_QUEUE_LEN 8
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/*
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* NOTE: Must have 256 phases with 256 bytes each.
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* Otherwise the DMA 1-byte write trick wouldn't work.
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*/
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#define LO_NUM_PHASES 256
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#define LO_PHASE_BITS 8
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#define LO_PHASE_WORDS (1 << (LO_PHASE_BITS - 2))
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#define STEP_BASE ((UINT_MAX + 1.0) / CLK_SYS_HZ)
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static uint32_t nco_step = (uint32_t)(STEP_BASE * INIT_FREQ) * 32 * LO_PHASE_WORDS;
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static uint32_t nco_null = 0;
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static uint32_t lo_phase[LO_NUM_PHASES][LO_PHASE_WORDS]
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__attribute__((__aligned__(LO_NUM_PHASES * 4 * LO_PHASE_WORDS)));
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static uint32_t nco_addr = (uint32_t)lo_phase;
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#define DECIMATE 16
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#define RX_BITS_DEPTH 10
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#define RX_WORDS (1 << (RX_BITS_DEPTH - 2))
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static uint32_t rx_cos[RX_WORDS] __attribute__((__aligned__(1 << RX_BITS_DEPTH)));
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static const uint32_t *rx_start = rx_cos;
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static const uint32_t *rx_end = rx_cos + RX_WORDS - 1;
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#define NUM_GAINS 29
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static int gains[NUM_GAINS] = { 0, 9, 14, 27, 37, 77, 87, 125, 144, 157,
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166, 197, 207, 229, 254, 280, 297, 328, 338, 364,
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372, 386, 402, 421, 434, 439, 445, 480, 496 };
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static int sample_rate = INIT_SAMPLE_RATE;
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static int dc_level = CLK_SYS_HZ / INIT_SAMPLE_RATE / 2;
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static int gain = INIT_GAIN;
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static int frequency = INIT_FREQ;
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static int dma_ch_rx1 = -1;
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static int dma_ch_rx2 = -1;
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static int dma_ch_nco1 = -1;
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static int dma_ch_nco2 = -1;
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static int dma_ch_nco3 = -1;
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static int dma_ch_mix = -1;
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static int dma_ch_samp_cos = -1;
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static int dma_t_samp = -1;
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static int dma_ch_in_cos = -1;
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static queue_t iq_queue;
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static uint8_t iq_queue_buffer[IQ_QUEUE_LEN][IQ_BLOCK_LEN];
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static size_t iq_queue_pos = 0;
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static uint32_t rnd = 0;
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static int origin_lo = -1;
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static int origin_rx = -1;
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static int origin_fb = -1;
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static int origin_ad = 0;
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inline static __unused uint32_t rnd_next()
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{
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rnd = rnd * 0x41c64e6d + 12345;
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return rnd;
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}
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static void dma_channel_clear_chain_to(int ch)
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{
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uint32_t ctrl = dma_hw->ch[ch].al1_ctrl;
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ctrl &= ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS;
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ctrl |= ch << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB;
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dma_hw->ch[ch].al1_ctrl = ctrl;
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}
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static void init_lo()
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{
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gpio_disable_pulls(LO_PIN);
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pio_gpio_init(PIO, LO_PIN);
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gpio_set_drive_strength(LO_PIN, GPIO_DRIVE_STRENGTH_12MA);
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gpio_set_slew_rate(LO_PIN, GPIO_SLEW_RATE_FAST);
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const uint16_t insn[] = {
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pio_encode_out(pio_pindirs, 1),
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};
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pio_program_t prog = {
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.instructions = insn,
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.length = sizeof(insn) / sizeof(*insn),
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.origin = origin_lo,
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};
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pio_sm_restart(PIO, SM_LO);
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pio_sm_clear_fifos(PIO, SM_LO);
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if (pio_can_add_program(PIO, &prog))
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origin_lo = pio_add_program(PIO, &prog);
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pio_sm_config pc = pio_get_default_sm_config();
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sm_config_set_out_pins(&pc, LO_PIN, 1);
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sm_config_set_set_pins(&pc, LO_PIN, 1);
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sm_config_set_wrap(&pc, origin_lo, origin_lo + prog.length - 1);
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sm_config_set_clkdiv_int_frac(&pc, 1, 0);
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sm_config_set_fifo_join(&pc, PIO_FIFO_JOIN_TX);
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sm_config_set_out_shift(&pc, false, true, 32);
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pio_sm_init(PIO, SM_LO, origin_lo, &pc);
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pio_sm_set_consecutive_pindirs(PIO, SM_LO, LO_PIN, 1, GPIO_IN);
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pio_sm_exec_wait_blocking(PIO, SM_LO, pio_encode_set(pio_pins, 0));
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}
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static void init_fb()
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{
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gpio_disable_pulls(FB_PIN);
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pio_gpio_init(PIO, FB_PIN);
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// NOTE: Not sure if this is ideal.
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hw_set_bits(&PIO->input_sync_bypass, 1u << RX_PIN);
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gpio_set_input_hysteresis_enabled(RX_PIN, false);
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gpio_set_drive_strength(FB_PIN, GPIO_DRIVE_STRENGTH_2MA);
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gpio_set_slew_rate(FB_PIN, GPIO_SLEW_RATE_SLOW);
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const uint16_t insn[] = {
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pio_encode_mov_not(pio_pins, pio_pins) | pio_encode_sideset(1, 1) |
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pio_encode_delay(0),
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//pio_encode_nop() | pio_encode_sideset(1, 0) | pio_encode_delay(0),
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};
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pio_program_t prog = {
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.instructions = insn,
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.length = sizeof(insn) / sizeof(*insn),
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.origin = origin_fb,
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};
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pio_sm_restart(PIO, SM_FB);
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pio_sm_clear_fifos(PIO, SM_FB);
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if (pio_can_add_program(PIO, &prog))
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origin_fb = pio_add_program(PIO, &prog);
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pio_sm_config pc = pio_get_default_sm_config();
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sm_config_set_sideset(&pc, 1, false, true);
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sm_config_set_in_pins(&pc, RX_PIN);
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sm_config_set_out_pins(&pc, FB_PIN, 1);
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sm_config_set_set_pins(&pc, FB_PIN, 1);
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sm_config_set_sideset_pins(&pc, FB_PIN);
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sm_config_set_wrap(&pc, origin_fb, origin_fb + prog.length - 1);
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sm_config_set_clkdiv_int_frac(&pc, 1, 0);
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pio_sm_init(PIO, SM_FB, origin_fb, &pc);
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pio_sm_set_consecutive_pindirs(PIO, SM_FB, FB_PIN, 1, GPIO_OUT);
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}
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static void init_rx()
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{
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gpio_disable_pulls(RX_PIN);
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pio_gpio_init(PIO, RX_PIN);
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const uint16_t insn[] = {
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pio_encode_in(pio_pins, 1) | pio_encode_delay(0),
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};
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pio_program_t prog = {
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.instructions = insn,
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.length = sizeof(insn) / sizeof(*insn),
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.origin = origin_rx,
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};
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pio_sm_restart(PIO, SM_RX);
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pio_sm_clear_fifos(PIO, SM_RX);
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if (pio_can_add_program(PIO, &prog))
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origin_rx = pio_add_program(PIO, &prog);
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pio_sm_config pc = pio_get_default_sm_config();
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sm_config_set_in_pins(&pc, RX_PIN);
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sm_config_set_wrap(&pc, origin_rx, origin_rx + prog.length - 1);
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sm_config_set_clkdiv_int_frac(&pc, 1, 0);
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sm_config_set_fifo_join(&pc, PIO_FIFO_JOIN_RX);
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sm_config_set_in_shift(&pc, false, true, 32);
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pio_sm_init(PIO, SM_RX, origin_rx, &pc);
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pio_sm_set_consecutive_pindirs(PIO, SM_RX, RX_PIN, 1, GPIO_IN);
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}
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static const uint32_t samp_insn = 16;
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static void init_ad()
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{
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const uint16_t insn[] = {
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pio_encode_out(pio_pc, 4), // 0000 +0
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pio_encode_jmp_x_dec(0), // 0001 +1
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pio_encode_jmp_x_dec(0), // 0010 +1
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pio_encode_jmp_y_dec(0), // 0011 +2
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pio_encode_jmp_x_dec(0), // 0100 +1
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pio_encode_jmp_y_dec(0), // 0101 +2
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pio_encode_jmp_y_dec(0), // 0110 +2
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pio_encode_jmp_y_dec(1), // 0111 +2 +1
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pio_encode_jmp_x_dec(0), // 1000 +1
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pio_encode_jmp_y_dec(0), // 1001 +2
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pio_encode_jmp_y_dec(0), // 1010 +2
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pio_encode_jmp_y_dec(1), // 1011 +2 +1
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pio_encode_jmp_y_dec(0), // 1100 +2
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pio_encode_jmp_y_dec(1), // 1101 +2 +1
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pio_encode_jmp_y_dec(1), // 1110 +2 +1
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pio_encode_jmp_y_dec(3), // 1111 +2 +2
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/*
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* Should wrap here.
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* Jump to this portion must be inserted from the outside.
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*/
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pio_encode_in(pio_y, 32),
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pio_encode_in(pio_x, 32),
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pio_encode_set(pio_y, 0),
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pio_encode_set(pio_x, 0),
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pio_encode_jmp_y_dec(21),
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pio_encode_jmp_x_dec(22),
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pio_encode_out(pio_pc, 4),
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};
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pio_program_t prog = {
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.instructions = insn,
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.length = sizeof(insn) / sizeof(*insn),
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.origin = origin_ad,
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};
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pio_sm_restart(PIO, SM_AD);
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pio_sm_clear_fifos(PIO, SM_AD);
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if (pio_can_add_program(PIO, &prog))
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pio_add_program(PIO, &prog);
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pio_sm_config pc = pio_get_default_sm_config();
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sm_config_set_wrap(&pc, origin_ad, origin_ad + 15);
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sm_config_set_clkdiv_int_frac(&pc, 1, 0);
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sm_config_set_in_shift(&pc, false, true, 32);
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sm_config_set_out_shift(&pc, false, true, 32);
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pio_sm_init(PIO, SM_AD, origin_ad, &pc);
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}
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static void lo_generate_phase(uint32_t *buf, size_t len, uint32_t step, uint32_t phase)
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{
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for (size_t i = 0; i < len; i++) {
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uint32_t bits = 0;
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for (int j = 0; j < 32; j++) {
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bits |= phase >> 31;
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bits <<= 1;
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phase += step;
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}
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buf[i] = bits;
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}
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}
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static void rx_lo_init(double freq)
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{
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uint32_t step = STEP_BASE * freq;
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for (uint32_t i = 0; i < LO_NUM_PHASES; i++)
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lo_generate_phase(lo_phase[i], LO_PHASE_WORDS, step, i << 24);
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nco_step = step * 32 * LO_PHASE_WORDS;
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}
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static void rf_rx_start()
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{
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dma_ch_rx1 = dma_claim_unused_channel(true);
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dma_ch_rx2 = dma_claim_unused_channel(true);
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dma_ch_nco1 = dma_claim_unused_channel(true);
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dma_ch_nco2 = dma_claim_unused_channel(true);
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dma_ch_nco3 = dma_claim_unused_channel(true);
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dma_ch_mix = dma_claim_unused_channel(true);
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dma_ch_samp_cos = dma_claim_unused_channel(true);
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dma_channel_config dma_conf;
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/* Copy PDM bitstream into decimator. */
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dma_conf = dma_channel_get_default_config(dma_ch_rx1);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_RX, GPIO_IN));
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channel_config_set_chain_to(&dma_conf, dma_ch_rx2);
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dma_channel_configure(dma_ch_rx1, &dma_conf, &PIO->txf[SM_AD], &PIO->rxf[SM_RX], UINT_MAX,
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false);
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dma_conf = dma_channel_get_default_config(dma_ch_rx2);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_RX, GPIO_IN));
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channel_config_set_chain_to(&dma_conf, dma_ch_rx1);
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dma_channel_configure(dma_ch_rx2, &dma_conf, &PIO->txf[SM_AD], &PIO->rxf[SM_RX], UINT_MAX,
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false);
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/* Step the NCO. */
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dma_conf = dma_channel_get_default_config(dma_ch_nco1);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_chain_to(&dma_conf, dma_ch_nco2);
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dma_channel_configure(dma_ch_nco1, &dma_conf, &nco_null, &nco_step, 1, false);
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/* DMA above will increment the phase accumulator. */
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dma_sniffer_enable(dma_ch_nco1, DMA_SNIFF_CTRL_CALC_VALUE_SUM, true);
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/* Prepare the phase address. */
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dma_conf = dma_channel_get_default_config(dma_ch_nco2);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_8);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_chain_to(&dma_conf, dma_ch_nco3);
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dma_channel_configure(dma_ch_nco2, &dma_conf, (uint8_t *)(&nco_addr) + 1,
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((uint8_t *)&dma_hw->sniff_data) + 3, 1, false);
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/* Trigger LO using the address. */
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dma_conf = dma_channel_get_default_config(dma_ch_nco3);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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dma_channel_configure(dma_ch_nco3, &dma_conf, &dma_hw->ch[dma_ch_mix].al3_read_addr_trig,
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&nco_addr, 1, false);
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/* Drive the LO capacitor. */
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dma_conf = dma_channel_get_default_config(dma_ch_mix);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, true);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_LO, GPIO_OUT));
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channel_config_set_chain_to(&dma_conf, dma_ch_nco1);
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dma_channel_configure(dma_ch_mix, &dma_conf, &PIO->txf[SM_LO], lo_phase, LO_PHASE_WORDS,
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false);
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/* Trigger accumulator values push. */
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dma_conf = dma_channel_get_default_config(dma_ch_samp_cos);
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channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_conf, false);
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channel_config_set_write_increment(&dma_conf, false);
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channel_config_set_high_priority(&dma_conf, true);
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channel_config_set_dreq(&dma_conf, dma_get_timer_dreq(dma_t_samp));
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dma_channel_configure(dma_ch_samp_cos, &dma_conf, &PIO->sm[SM_AD].instr, &samp_insn,
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UINT_MAX, false);
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init_ad();
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init_lo();
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init_fb();
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init_rx();
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dma_channel_start(dma_ch_rx1);
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dma_channel_start(dma_ch_nco1);
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dma_channel_start(dma_ch_samp_cos);
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pio_set_sm_mask_enabled(PIO, 0x0f, true);
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}
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static void rf_rx_stop(void)
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{
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pio_set_sm_mask_enabled(PIO, 0x0f, false);
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sleep_us(10);
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dma_channel_clear_chain_to(dma_ch_rx1);
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dma_channel_clear_chain_to(dma_ch_rx2);
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dma_channel_clear_chain_to(dma_ch_nco1);
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dma_channel_clear_chain_to(dma_ch_nco2);
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dma_channel_clear_chain_to(dma_ch_nco3);
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dma_channel_clear_chain_to(dma_ch_mix);
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dma_channel_clear_chain_to(dma_ch_samp_cos);
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dma_channel_abort(dma_ch_rx1);
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dma_channel_abort(dma_ch_rx2);
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dma_channel_abort(dma_ch_nco1);
|
|
dma_channel_abort(dma_ch_nco2);
|
|
dma_channel_abort(dma_ch_nco3);
|
|
dma_channel_abort(dma_ch_mix);
|
|
dma_channel_abort(dma_ch_samp_cos);
|
|
|
|
dma_channel_cleanup(dma_ch_rx1);
|
|
dma_channel_cleanup(dma_ch_rx2);
|
|
dma_channel_cleanup(dma_ch_nco1);
|
|
dma_channel_cleanup(dma_ch_nco2);
|
|
dma_channel_cleanup(dma_ch_nco3);
|
|
dma_channel_cleanup(dma_ch_mix);
|
|
dma_channel_cleanup(dma_ch_samp_cos);
|
|
|
|
dma_channel_unclaim(dma_ch_rx1);
|
|
dma_channel_unclaim(dma_ch_rx2);
|
|
dma_channel_unclaim(dma_ch_nco1);
|
|
dma_channel_unclaim(dma_ch_nco2);
|
|
dma_channel_unclaim(dma_ch_nco3);
|
|
dma_channel_unclaim(dma_ch_mix);
|
|
dma_channel_unclaim(dma_ch_samp_cos);
|
|
|
|
dma_ch_rx1 = -1;
|
|
dma_ch_rx2 = -1;
|
|
dma_ch_nco1 = -1;
|
|
dma_ch_nco2 = -1;
|
|
dma_ch_nco3 = -1;
|
|
dma_ch_mix = -1;
|
|
dma_ch_samp_cos = -1;
|
|
}
|
|
|
|
struct IQ {
|
|
int I, Q;
|
|
};
|
|
|
|
inline static int get_next_sample()
|
|
{
|
|
static const uint32_t *tail = rx_cos;
|
|
|
|
const uint32_t *head = (const uint32_t *)dma_hw->ch[dma_ch_in_cos].write_addr;
|
|
|
|
while (head == tail) {
|
|
asm volatile("nop; nop; nop; nop");
|
|
head = (const uint32_t *)dma_hw->ch[dma_ch_in_cos].write_addr;
|
|
}
|
|
|
|
int value = -(*tail++);
|
|
value *= 2;
|
|
value -= *tail++;
|
|
|
|
if (tail > rx_end)
|
|
tail = rx_start;
|
|
|
|
return gain * value - dc_level;
|
|
}
|
|
|
|
inline static struct IQ next_sample()
|
|
{
|
|
int I = 0, Q = 0;
|
|
|
|
int x15 = get_next_sample();
|
|
I += 93 * x15;
|
|
Q += 39 * x15;
|
|
|
|
int x14 = get_next_sample();
|
|
I += 71 * x14;
|
|
Q += 71 * x14;
|
|
|
|
int x13 = get_next_sample();
|
|
I += 39 * x13;
|
|
Q += 93 * x13;
|
|
|
|
int x12 = get_next_sample();
|
|
I += 0 * x12;
|
|
Q += 101 * x12;
|
|
|
|
int x11 = get_next_sample();
|
|
I += -39 * x11;
|
|
Q += 93 * x11;
|
|
|
|
int x10 = get_next_sample();
|
|
I += -71 * x10;
|
|
Q += 71 * x10;
|
|
|
|
int x09 = get_next_sample();
|
|
I += -93 * x09;
|
|
Q += 39 * x09;
|
|
|
|
int x08 = get_next_sample();
|
|
I += -101 * x08;
|
|
Q += 0 * x08;
|
|
|
|
int x07 = get_next_sample();
|
|
I += -93 * x07;
|
|
Q += -39 * x07;
|
|
|
|
int x06 = get_next_sample();
|
|
I += -71 * x06;
|
|
Q += -71 * x06;
|
|
|
|
int x05 = get_next_sample();
|
|
I += -39 * x05;
|
|
Q += -93 * x05;
|
|
|
|
int x04 = get_next_sample();
|
|
I += 0 * x04;
|
|
Q += -101 * x04;
|
|
|
|
int x03 = get_next_sample();
|
|
I += 39 * x03;
|
|
Q += -93 * x03;
|
|
|
|
int x02 = get_next_sample();
|
|
I += 71 * x02;
|
|
Q += -71 * x02;
|
|
|
|
int x01 = get_next_sample();
|
|
I += 93 * x01;
|
|
Q += -39 * x01;
|
|
|
|
int x00 = get_next_sample();
|
|
I += 101 * x00;
|
|
Q += 0 * x00;
|
|
|
|
I /= 1024;
|
|
Q /= 1024;
|
|
|
|
return (struct IQ){ I, Q };
|
|
}
|
|
|
|
static void rf_rx(void)
|
|
{
|
|
while (true) {
|
|
if (multicore_fifo_rvalid()) {
|
|
multicore_fifo_pop_blocking();
|
|
multicore_fifo_push_blocking(0);
|
|
return;
|
|
}
|
|
|
|
uint8_t *block = iq_queue_buffer[iq_queue_pos];
|
|
uint8_t *blockptr = block;
|
|
|
|
for (int i = 0; i < IQ_SAMPLES; i++) {
|
|
struct IQ IQ = next_sample();
|
|
int64_t I = IQ.I;
|
|
int64_t Q = IQ.Q;
|
|
|
|
I /= dc_level;
|
|
|
|
if (I > 127)
|
|
I = 127;
|
|
else if (I < -128)
|
|
I = -128;
|
|
|
|
*blockptr++ = (uint8_t)I + 128;
|
|
|
|
Q /= dc_level;
|
|
|
|
if (Q > 127)
|
|
Q = 127;
|
|
else if (Q < -128)
|
|
Q = -128;
|
|
|
|
*blockptr++ = (uint8_t)Q + 128;
|
|
}
|
|
|
|
if (queue_try_add(&iq_queue, &block)) {
|
|
iq_queue_pos = (iq_queue_pos + 1) & (IQ_QUEUE_LEN - 1);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void run_command(uint8_t cmd, uint32_t arg)
|
|
{
|
|
if (0x01 == cmd) {
|
|
/* Tune to a new center frequency */
|
|
frequency = arg;
|
|
rx_lo_init(frequency + sample_rate);
|
|
} else if (0x02 == cmd) {
|
|
/* Set the rate at which IQ sample pairs are sent */
|
|
sample_rate = arg;
|
|
dc_level = CLK_SYS_HZ / sample_rate / 2;
|
|
dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / (sample_rate * DECIMATE));
|
|
rx_lo_init(frequency + sample_rate);
|
|
} else if (0x04 == cmd) {
|
|
/* Set the tuner gain level */
|
|
gain = INIT_GAIN * powf(10.0f, arg / 200.0f);
|
|
} else if (0x0d == cmd) {
|
|
/* Set tuner gain by the tuner's gain index */
|
|
|
|
if (arg >= NUM_GAINS)
|
|
arg = NUM_GAINS - 1;
|
|
|
|
gain = INIT_GAIN * powf(10.0f, gains[arg] / 200.0f);
|
|
}
|
|
}
|
|
|
|
static int check_command(void)
|
|
{
|
|
static uint8_t buf[5];
|
|
static int pos = 0;
|
|
|
|
int c;
|
|
|
|
while ((c = getchar_timeout_us(0)) >= 0) {
|
|
if (0 == pos && 0 == c)
|
|
return 0;
|
|
|
|
buf[pos++] = c;
|
|
|
|
if (5 == pos) {
|
|
uint32_t arg = (buf[1] << 24) | (buf[2] << 16) | (buf[3] << 8) | buf[4];
|
|
run_command(buf[0], arg);
|
|
pos = 0;
|
|
return buf[0];
|
|
}
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static void do_rx()
|
|
{
|
|
rf_rx_start();
|
|
sleep_us(100);
|
|
|
|
dma_ch_in_cos = dma_claim_unused_channel(true);
|
|
|
|
dma_channel_config dma_conf;
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_in_cos);
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
channel_config_set_write_increment(&dma_conf, true);
|
|
channel_config_set_ring(&dma_conf, GPIO_OUT, RX_BITS_DEPTH);
|
|
channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_AD, false));
|
|
dma_channel_configure(dma_ch_in_cos, &dma_conf, rx_cos, &PIO->rxf[SM_AD], UINT_MAX, true);
|
|
|
|
multicore_launch_core1(rf_rx);
|
|
|
|
const uint8_t *block;
|
|
|
|
while (queue_try_remove(&iq_queue, &block))
|
|
/* Flush the queue */;
|
|
|
|
while (true) {
|
|
int cmd;
|
|
|
|
while ((cmd = check_command()) >= 0)
|
|
if (0 == cmd)
|
|
goto done;
|
|
|
|
if (queue_try_remove(&iq_queue, &block)) {
|
|
fwrite(block, IQ_BLOCK_LEN, 1, stdout);
|
|
fflush(stdout);
|
|
} else {
|
|
int wait = rnd_next() & 0x1fff;
|
|
|
|
for (int i = 0; i < wait; i++)
|
|
asm volatile("nop");
|
|
}
|
|
}
|
|
|
|
done:
|
|
multicore_fifo_push_blocking(0);
|
|
multicore_fifo_pop_blocking();
|
|
sleep_us(10);
|
|
multicore_reset_core1();
|
|
|
|
rf_rx_stop();
|
|
|
|
dma_channel_clear_chain_to(dma_ch_in_cos);
|
|
dma_channel_abort(dma_ch_in_cos);
|
|
dma_channel_cleanup(dma_ch_in_cos);
|
|
dma_channel_unclaim(dma_ch_in_cos);
|
|
dma_ch_in_cos = -1;
|
|
}
|
|
|
|
int main()
|
|
{
|
|
vreg_set_voltage(VREG_VOLTAGE);
|
|
set_sys_clock_khz(CLK_SYS_HZ / KHZ, true);
|
|
clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, CLK_SYS_HZ,
|
|
CLK_SYS_HZ);
|
|
|
|
/* Enable PSU PWM mode. */
|
|
gpio_init(PSU_PIN);
|
|
gpio_set_dir(PSU_PIN, GPIO_OUT);
|
|
gpio_put(PSU_PIN, 1);
|
|
|
|
bus_ctrl_hw->priority |= BUSCTRL_BUS_PRIORITY_DMA_W_BITS | BUSCTRL_BUS_PRIORITY_DMA_R_BITS;
|
|
|
|
stdio_usb_init();
|
|
setvbuf(stdout, NULL, _IONBF, 0);
|
|
|
|
queue_init(&iq_queue, sizeof(uint8_t *), IQ_QUEUE_LEN);
|
|
|
|
rx_lo_init(frequency + sample_rate);
|
|
|
|
dma_t_samp = dma_claim_unused_timer(true);
|
|
dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / (sample_rate * DECIMATE));
|
|
|
|
while (true) {
|
|
if (check_command() > 0) {
|
|
static const uint32_t header[3] = { __builtin_bswap32(0x52544c30),
|
|
__builtin_bswap32(5),
|
|
__builtin_bswap32(NUM_GAINS) };
|
|
fwrite(header, sizeof header, 1, stdout);
|
|
fflush(stdout);
|
|
|
|
do_rx();
|
|
}
|
|
|
|
sleep_ms(10);
|
|
}
|
|
}
|