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@ -4,6 +4,7 @@
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#include <pico/util/queue.h>
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#include <hardware/clocks.h>
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#include <hardware/adc.h>
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#include <hardware/dma.h>
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#include <hardware/gpio.h>
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#include <hardware/pll.h>
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@ -22,60 +23,55 @@
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#include <stdlib.h>
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#define VREG_VOLTAGE VREG_VOLTAGE_1_20
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#define CLK_SYS_HZ (300 * MHZ)
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#define CLK_SYS_HZ (288 * MHZ)
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#define INIT_SAMPLE_RATE 200000
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#define INIT_FREQ 94600000
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#define INIT_GAIN 127
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#define LO_PIN 21
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#define RX_PIN 26
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#define PSU_PIN 23
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#define PIO pio1
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#define SM_LO 0
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#define IQ_SAMPLES 32
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#define IQ_BLOCK_LEN (2 * IQ_SAMPLES)
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#define IQ_QUEUE_LEN 4
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#define XOR_ADDR 0x1000
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#define LO_COS_ACCUMULATOR (&pio1->sm[2].pinctrl)
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#define LO_SIN_ACCUMULATOR (&pio1->sm[3].pinctrl)
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#define LO_BITS_DEPTH 15
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#define LO_WORDS (1 << (LO_BITS_DEPTH - 2))
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static uint32_t lo_cos[LO_WORDS] __attribute__((__aligned__(1 << LO_BITS_DEPTH)));
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static uint32_t lo_sin[LO_WORDS] __attribute__((__aligned__(1 << LO_BITS_DEPTH)));
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#define IQ_QUEUE_LEN 8
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#define ADC_RATE (2 * MHZ)
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#define DECIMATE 4
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#define RX_STRIDE (2 * IQ_SAMPLES * DECIMATE)
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#define RX_BITS_DEPTH 13
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#define RX_WORDS (1 << (RX_BITS_DEPTH - 2))
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static_assert(RX_STRIDE * 4 < RX_WORDS, "RX_STRIDE * 4 < RX_WORDS");
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#define NCO_NUM_PHASES (1 << 8)
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#define NCO_PHASE_BITS 8
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#define NCO_PHASE_WORDS (1 << (NCO_PHASE_BITS - 2))
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#define STEP_BASE ((UINT_MAX + 1.0) / CLK_SYS_HZ)
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static uint32_t rx_cos[RX_WORDS] __attribute__((__aligned__(1 << RX_BITS_DEPTH)));
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static uint32_t rx_sin[RX_WORDS] __attribute__((__aligned__(1 << RX_BITS_DEPTH)));
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static uint32_t nco_step = (uint32_t)(STEP_BASE * INIT_FREQ) * 32 * NCO_PHASE_WORDS;
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static uint32_t nco_null = 0;
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static uint32_t nco_mask = (1 << NCO_PHASE_BITS) - 1;
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#define INIT_SAMPLE_RATE 100000
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#define INIT_FREQ 94600000
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static uint32_t nco_phase[NCO_NUM_PHASES][NCO_PHASE_WORDS]
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__attribute__((__aligned__(NCO_NUM_PHASES * 4 * NCO_PHASE_WORDS)));
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static_assert(sizeof(nco_phase) == 65536, "sizeof(nco_phase) == 65536");
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static uint32_t *nco_addr = &nco_phase[0][0];
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#define NUM_GAINS 29
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static int gains[NUM_GAINS] = { 0, 9, 14, 27, 37, 77, 87, 125, 144, 157,
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166, 197, 207, 229, 254, 280, 297, 328, 338, 364,
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372, 386, 402, 421, 434, 439, 445, 480, 496 };
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static int sample_rate = INIT_SAMPLE_RATE;
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static int gain = INIT_GAIN;
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static int frequency = INIT_FREQ;
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#define SIN_PHASE (0u)
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#define COS_PHASE (3u << 30)
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/* rx -> cp -> cos -> sin -> pio_cos -> pio_sin -> rx ... */
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static int dma_ch_rx = -1;
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static int dma_ch_cp = -1;
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static int dma_ch_cos = -1;
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static int dma_ch_sin = -1;
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static int dma_ch_pio_cos = -1;
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static int dma_ch_pio_sin = -1;
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static int dma_ch_samp_trig = -1;
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static int dma_ch_samp_cos = -1;
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static int dma_ch_samp_sin = -1;
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static int dma_t_samp = -1;
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static int dma_ch_in_cos = -1;
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static int dma_ch_in_sin = -1;
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static int dma_ch_nco1 = -1;
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static int dma_ch_nco2 = -1;
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static int dma_ch_nco3 = -1;
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static int dma_ch_nco4 = -1;
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static int dma_ch_mix = -1;
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static queue_t iq_queue;
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static uint8_t iq_queue_buffer[IQ_QUEUE_LEN][IQ_BLOCK_LEN];
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@ -83,404 +79,245 @@ static size_t iq_queue_pos = 0;
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static uint32_t rnd = 0;
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inline static uint32_t rnd_next()
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static int origin_lo = -1;
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inline static __unused uint32_t rnd_next()
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{
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rnd = rnd * 0x41c64e6d + 12345;
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return rnd;
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}
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static void bias_set_gain(int gain)
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static void dma_channel_clear_chain_to(int ch)
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{
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if (gain > 9)
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gain = 9;
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else if (gain < 0)
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gain = 0;
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pio1->sm[0].execctrl = (pio1->sm[0].execctrl & ~PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS) |
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((19 - gain) << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB);
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uint32_t ctrl = dma_hw->ch[ch].al1_ctrl;
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ctrl &= ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS;
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ctrl |= ch << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB;
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dma_hw->ch[ch].al1_ctrl = ctrl;
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}
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static void bias_init(int in_pin, int out_pin)
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static void init_lo()
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{
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gpio_disable_pulls(in_pin);
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gpio_disable_pulls(out_pin);
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gpio_disable_pulls(LO_PIN);
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pio_gpio_init(PIO, LO_PIN);
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pio_gpio_init(pio1, out_pin);
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gpio_set_input_hysteresis_enabled(in_pin, false);
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gpio_set_drive_strength(out_pin, GPIO_DRIVE_STRENGTH_2MA);
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gpio_set_slew_rate(out_pin, GPIO_SLEW_RATE_SLOW);
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gpio_set_drive_strength(LO_PIN, GPIO_DRIVE_STRENGTH_12MA);
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gpio_set_slew_rate(LO_PIN, GPIO_SLEW_RATE_FAST);
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const uint16_t insn[] = {
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pio_encode_in(pio_pins, 1),
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pio_encode_in(pio_pins, 1),
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pio_encode_in(pio_pins, 1),
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pio_encode_in(pio_pins, 1),
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pio_encode_in(pio_pins, 1),
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pio_encode_in(pio_pins, 1),
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pio_encode_in(pio_pins, 1),
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pio_encode_in(pio_pins, 1),
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pio_encode_in(pio_pins, 1),
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pio_encode_mov(pio_x, pio_isr),
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pio_encode_mov(pio_isr, pio_null),
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pio_encode_jmp_x_dec(11),
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pio_encode_mov_not(pio_pins, pio_pins) | pio_encode_sideset(1, 1),
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pio_encode_out(pio_pindirs, 1),
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};
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pio_program_t prog = {
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.instructions = insn,
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.length = sizeof(insn) / sizeof(*insn),
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.origin = 10,
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.origin = origin_lo,
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};
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pio_sm_set_enabled(pio1, 0, false);
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pio_sm_restart(pio1, 0);
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pio_sm_clear_fifos(pio1, 0);
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pio_sm_restart(PIO, SM_LO);
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pio_sm_clear_fifos(PIO, SM_LO);
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if (pio_can_add_program(pio1, &prog))
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pio_add_program(pio1, &prog);
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if (pio_can_add_program(PIO, &prog))
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origin_lo = pio_add_program(PIO, &prog);
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pio_sm_config pc = pio_get_default_sm_config();
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sm_config_set_in_shift(&pc, false, false, 32);
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sm_config_set_sideset(&pc, 1, false, true);
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sm_config_set_sideset_pins(&pc, out_pin);
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sm_config_set_in_pins(&pc, in_pin);
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sm_config_set_out_pins(&pc, out_pin, 1);
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sm_config_set_set_pins(&pc, out_pin, 1);
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sm_config_set_wrap(&pc, prog.origin, prog.origin + prog.length - 1);
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sm_config_set_out_pins(&pc, LO_PIN, 1);
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sm_config_set_set_pins(&pc, LO_PIN, 1);
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sm_config_set_wrap(&pc, origin_lo, origin_lo + prog.length - 1);
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sm_config_set_clkdiv_int_frac(&pc, 1, 0);
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pio_sm_init(pio1, 0, prog.origin, &pc);
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pio_sm_set_consecutive_pindirs(pio1, 0, out_pin, 1, GPIO_OUT);
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pio_sm_set_enabled(pio1, 0, true);
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}
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static void watch_init(int in_pin)
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{
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const uint16_t insn[] = {
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pio_encode_in(pio_pins, 1),
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};
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pio_program_t prog = {
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.instructions = insn,
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.length = 1,
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.origin = 6,
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};
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pio_sm_set_enabled(pio1, 1, false);
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pio_sm_restart(pio1, 1);
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pio_sm_clear_fifos(pio1, 1);
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if (pio_can_add_program(pio1, &prog))
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pio_add_program(pio1, &prog);
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pio_sm_config pc = pio_get_default_sm_config();
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sm_config_set_in_pins(&pc, in_pin);
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sm_config_set_wrap(&pc, prog.origin, prog.origin + prog.length - 1);
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sm_config_set_clkdiv_int_frac(&pc, 1, 0);
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sm_config_set_fifo_join(&pc, PIO_FIFO_JOIN_RX);
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sm_config_set_in_shift(&pc, false, true, 32);
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pio_sm_init(pio1, 1, prog.origin, &pc);
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pio_sm_set_enabled(pio1, 1, true);
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}
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static void adder_init()
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{
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const uint16_t insn[] = {
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pio_encode_jmp_y_dec(1),
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pio_encode_out(pio_pc, 2),
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pio_encode_out(pio_pc, 2),
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pio_encode_jmp_x_dec(2),
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/* Avoid Y-- on wrap. */
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pio_encode_out(pio_pc, 2),
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};
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pio_program_t prog = {
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.instructions = insn,
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.length = sizeof(insn) / sizeof(*insn),
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.origin = 0,
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};
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pio_sm_set_enabled(pio1, 2, false);
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pio_sm_set_enabled(pio1, 3, false);
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pio_sm_restart(pio1, 2);
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pio_sm_restart(pio1, 3);
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pio_sm_clear_fifos(pio1, 2);
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pio_sm_clear_fifos(pio1, 3);
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if (pio_can_add_program(pio1, &prog))
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pio_add_program(pio1, &prog);
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pio_sm_config pc = pio_get_default_sm_config();
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sm_config_set_wrap(&pc, prog.origin, prog.origin + prog.length - 1);
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sm_config_set_clkdiv_int_frac(&pc, 1, 0);
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sm_config_set_in_shift(&pc, false, true, 32);
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sm_config_set_fifo_join(&pc, PIO_FIFO_JOIN_TX);
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sm_config_set_out_shift(&pc, false, true, 32);
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pio_sm_init(pio1, 2, prog.origin + prog.length - 1, &pc);
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pio_sm_init(pio1, 3, prog.origin + prog.length - 1, &pc);
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pio_sm_init(PIO, SM_LO, origin_lo, &pc);
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pio_sm_set_enabled(pio1, 2, true);
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pio_sm_set_enabled(pio1, 3, true);
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pio_sm_set_consecutive_pindirs(PIO, SM_LO, LO_PIN, 1, GPIO_IN);
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pio_sm_exec_wait_blocking(PIO, SM_LO, pio_encode_set(pio_pins, 0));
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}
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#define STEP_BASE ((UINT_MAX + 1.0) / CLK_SYS_HZ)
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static uint32_t freq_step = 1;
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static void lo_generate(uint32_t *buf, double freq, uint32_t phase)
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inline static uint32_t phase_bit(uint32_t phase, uint32_t step)
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{
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freq_step = STEP_BASE * freq;
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uint32_t next = phase + step;
|
|
|
|
|
|
|
|
|
|
unsigned down = 2 + __builtin_clz(freq_step);
|
|
|
|
|
if ((next & 0x7fffffff) > (step >> 1))
|
|
|
|
|
return next >> 31;
|
|
|
|
|
|
|
|
|
|
for (size_t i = 0; i < LO_WORDS; i++) {
|
|
|
|
|
return phase >> 31;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nco_generate_phase(uint32_t *buf, size_t len, uint32_t step, uint32_t phase)
|
|
|
|
|
{
|
|
|
|
|
for (size_t i = 0; i < len; i++) {
|
|
|
|
|
uint32_t bits = 0;
|
|
|
|
|
int shift = (rnd_next() >> down) - (rnd_next() >> down);
|
|
|
|
|
|
|
|
|
|
for (int j = 0; j < 32; j++) {
|
|
|
|
|
bits |= (phase + shift) >> 31;
|
|
|
|
|
bits |= phase_bit(phase, step);
|
|
|
|
|
bits <<= 1;
|
|
|
|
|
phase += freq_step;
|
|
|
|
|
phase += step;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
buf[i] = bits;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void lo_tweak(uint32_t *buf, uint32_t phase)
|
|
|
|
|
static void rx_lo_init(double freq)
|
|
|
|
|
{
|
|
|
|
|
static size_t i = 0;
|
|
|
|
|
uint32_t bits = 0;
|
|
|
|
|
unsigned down = 2 + __builtin_clz(freq_step);
|
|
|
|
|
uint32_t step = STEP_BASE * freq;
|
|
|
|
|
|
|
|
|
|
phase += freq_step * i * 32;
|
|
|
|
|
for (uint32_t i = 0; i < NCO_NUM_PHASES; i++)
|
|
|
|
|
nco_generate_phase(nco_phase[i], NCO_PHASE_WORDS, step,
|
|
|
|
|
i << (__builtin_clz(NCO_NUM_PHASES) + 1));
|
|
|
|
|
|
|
|
|
|
for (int j = 0; j < 32; j++) {
|
|
|
|
|
int shift = (rnd_next() >> down) - (rnd_next() >> down);
|
|
|
|
|
bits |= (phase + shift) >> 31;
|
|
|
|
|
bits <<= 1;
|
|
|
|
|
phase += freq_step;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
buf[i] = bits;
|
|
|
|
|
i = (i + 1) & (LO_WORDS - 1);
|
|
|
|
|
nco_step = step * 32 * NCO_PHASE_WORDS;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rx_lo_init(double req_freq, bool align)
|
|
|
|
|
static void rf_rx_start()
|
|
|
|
|
{
|
|
|
|
|
const double step_hz = (double)CLK_SYS_HZ / (8 << LO_BITS_DEPTH);
|
|
|
|
|
double freq = req_freq;
|
|
|
|
|
|
|
|
|
|
if (align)
|
|
|
|
|
freq = round(freq / step_hz) * step_hz;
|
|
|
|
|
|
|
|
|
|
lo_generate(lo_cos, freq, COS_PHASE);
|
|
|
|
|
lo_generate(lo_sin, freq, SIN_PHASE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const uint32_t samp_insn[4] __attribute__((__aligned__(16)));
|
|
|
|
|
static const uint32_t samp_insn[4] = {
|
|
|
|
|
0x4040, /* IN Y, 32 */
|
|
|
|
|
0x4020, /* IN X, 32 */
|
|
|
|
|
0xe040, /* SET Y, 0 */
|
|
|
|
|
0xe020, /* SET X, 0 */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static uint32_t null, one = 1;
|
|
|
|
|
|
|
|
|
|
static void rf_rx_start(int rx_pin, int bias_pin)
|
|
|
|
|
{
|
|
|
|
|
dma_ch_rx = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_cp = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_cos = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_sin = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_pio_cos = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_pio_sin = dma_claim_unused_channel(true);
|
|
|
|
|
|
|
|
|
|
dma_ch_samp_cos = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_samp_sin = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_samp_trig = dma_claim_unused_channel(true);
|
|
|
|
|
|
|
|
|
|
dma_t_samp = dma_claim_unused_timer(true);
|
|
|
|
|
dma_ch_nco1 = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_nco2 = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_nco3 = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_nco4 = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_mix = dma_claim_unused_channel(true);
|
|
|
|
|
|
|
|
|
|
dma_channel_config dma_conf;
|
|
|
|
|
|
|
|
|
|
/* Read received word into accumulator I. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_rx);
|
|
|
|
|
/* Step the NCO. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_nco1);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_dreq(&dma_conf, pio_get_dreq(pio1, 1, false));
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_cp);
|
|
|
|
|
dma_channel_configure(dma_ch_rx, &dma_conf, LO_COS_ACCUMULATOR, &pio1->rxf[1], 1, false);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_nco2);
|
|
|
|
|
dma_channel_configure(dma_ch_nco1, &dma_conf, &nco_null, &nco_step, 1, false);
|
|
|
|
|
|
|
|
|
|
/* Copy accumulator I to accumulator Q. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_cp);
|
|
|
|
|
/* DMA above will increment the phase accumulator. */
|
|
|
|
|
dma_sniffer_enable(dma_ch_nco1, DMA_SNIFF_CTRL_CALC_VALUE_SUM, true);
|
|
|
|
|
|
|
|
|
|
/* Prepare the phase address. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_nco2);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_16);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_nco3);
|
|
|
|
|
dma_channel_configure(dma_ch_nco2, &dma_conf, (void *)(&nco_addr) + 0,
|
|
|
|
|
((void *)&dma_hw->sniff_data) + 2, 1, false);
|
|
|
|
|
|
|
|
|
|
/* Copy it to the DMA. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_nco3);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_cos);
|
|
|
|
|
dma_channel_configure(dma_ch_cp, &dma_conf, LO_SIN_ACCUMULATOR, LO_COS_ACCUMULATOR, 1,
|
|
|
|
|
false);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_nco4);
|
|
|
|
|
dma_channel_configure(dma_ch_nco3, &dma_conf, &dma_hw->ch[dma_ch_mix].read_addr, &nco_addr,
|
|
|
|
|
1, false);
|
|
|
|
|
|
|
|
|
|
/* Read lo_cos into accumulator I with XOR. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_cos);
|
|
|
|
|
/* Trigger LO by clearing the bottom bits. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_nco4);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
dma_channel_configure(dma_ch_nco4, &dma_conf,
|
|
|
|
|
(void *)&dma_hw->ch[dma_ch_mix].al3_read_addr_trig +
|
|
|
|
|
REG_ALIAS_CLR_BITS,
|
|
|
|
|
&nco_mask, 1, false);
|
|
|
|
|
|
|
|
|
|
/* Drive the LO capacitor. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_mix);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, true);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_ring(&dma_conf, false, LO_BITS_DEPTH);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_sin);
|
|
|
|
|
dma_channel_configure(dma_ch_cos, &dma_conf, LO_COS_ACCUMULATOR + XOR_ADDR / 4, lo_cos, 1,
|
|
|
|
|
false);
|
|
|
|
|
channel_config_set_dreq(&dma_conf, pio_get_dreq(PIO, SM_LO, GPIO_OUT));
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_nco1);
|
|
|
|
|
dma_channel_configure(dma_ch_mix, &dma_conf, &PIO->txf[SM_LO], &nco_phase[0][0],
|
|
|
|
|
NCO_PHASE_WORDS, false);
|
|
|
|
|
|
|
|
|
|
/* Read lo_sin into accumulator Q with XOR. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_sin);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, true);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_ring(&dma_conf, false, LO_BITS_DEPTH);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_pio_cos);
|
|
|
|
|
dma_channel_configure(dma_ch_sin, &dma_conf, LO_SIN_ACCUMULATOR + XOR_ADDR / 4, lo_sin, 1,
|
|
|
|
|
false);
|
|
|
|
|
init_lo();
|
|
|
|
|
|
|
|
|
|
/* Copy mixed I accumulator to PIO adder I. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_pio_cos);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_dreq(&dma_conf, pio_get_dreq(pio1, 2, true));
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_pio_sin);
|
|
|
|
|
dma_channel_configure(dma_ch_pio_cos, &dma_conf, &pio1->txf[2], LO_COS_ACCUMULATOR, 1,
|
|
|
|
|
false);
|
|
|
|
|
dma_channel_start(dma_ch_nco1);
|
|
|
|
|
|
|
|
|
|
/* Copy mixed Q accumulator to PIO adder Q. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_pio_sin);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_dreq(&dma_conf, pio_get_dreq(pio1, 3, true));
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_rx);
|
|
|
|
|
dma_channel_configure(dma_ch_pio_sin, &dma_conf, &pio1->txf[3], LO_SIN_ACCUMULATOR, 1,
|
|
|
|
|
false);
|
|
|
|
|
|
|
|
|
|
/* Pacing timer for the sampling script trigger channel. */
|
|
|
|
|
dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / (sample_rate * DECIMATE));
|
|
|
|
|
|
|
|
|
|
/* Sampling trigger channel. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_samp_trig);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_dreq(&dma_conf, dma_get_timer_dreq(dma_t_samp));
|
|
|
|
|
channel_config_set_high_priority(&dma_conf, true);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_samp_cos);
|
|
|
|
|
dma_channel_configure(dma_ch_samp_trig, &dma_conf, &null, &one, 1, false);
|
|
|
|
|
|
|
|
|
|
/* Trigger I accumulator values push. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_samp_cos);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, true);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_ring(&dma_conf, false, 4);
|
|
|
|
|
channel_config_set_high_priority(&dma_conf, true);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_samp_sin);
|
|
|
|
|
dma_channel_configure(dma_ch_samp_cos, &dma_conf, &pio1->sm[2].instr, samp_insn, 4, false);
|
|
|
|
|
|
|
|
|
|
/* Trigger Q accumulator values push. */
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_samp_sin);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, true);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_ring(&dma_conf, false, 4);
|
|
|
|
|
channel_config_set_high_priority(&dma_conf, true);
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_samp_trig);
|
|
|
|
|
dma_channel_configure(dma_ch_samp_sin, &dma_conf, &pio1->sm[3].instr, samp_insn, 4, false);
|
|
|
|
|
|
|
|
|
|
bias_init(rx_pin, bias_pin);
|
|
|
|
|
adder_init();
|
|
|
|
|
|
|
|
|
|
dma_channel_start(dma_ch_rx);
|
|
|
|
|
dma_channel_start(dma_ch_samp_trig);
|
|
|
|
|
watch_init(rx_pin);
|
|
|
|
|
pio_sm_set_enabled(PIO, SM_LO, true);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rf_rx_stop(void)
|
|
|
|
|
{
|
|
|
|
|
pio_sm_set_enabled(pio1, 0, false);
|
|
|
|
|
pio_sm_set_enabled(pio1, 1, false);
|
|
|
|
|
pio_sm_set_enabled(pio1, 2, false);
|
|
|
|
|
pio_sm_set_enabled(pio1, 3, false);
|
|
|
|
|
|
|
|
|
|
pio_sm_restart(pio1, 0);
|
|
|
|
|
pio_sm_restart(pio1, 1);
|
|
|
|
|
pio_sm_restart(pio1, 2);
|
|
|
|
|
pio_sm_restart(pio1, 3);
|
|
|
|
|
|
|
|
|
|
pio_sm_clear_fifos(pio1, 0);
|
|
|
|
|
pio_sm_clear_fifos(pio1, 1);
|
|
|
|
|
pio_sm_clear_fifos(pio1, 2);
|
|
|
|
|
pio_sm_clear_fifos(pio1, 3);
|
|
|
|
|
pio_sm_set_enabled(PIO, SM_LO, false);
|
|
|
|
|
|
|
|
|
|
sleep_us(10);
|
|
|
|
|
|
|
|
|
|
dma_channel_abort(dma_ch_rx);
|
|
|
|
|
dma_channel_abort(dma_ch_cp);
|
|
|
|
|
dma_channel_abort(dma_ch_cos);
|
|
|
|
|
dma_channel_abort(dma_ch_sin);
|
|
|
|
|
dma_channel_abort(dma_ch_pio_cos);
|
|
|
|
|
dma_channel_abort(dma_ch_pio_sin);
|
|
|
|
|
dma_channel_abort(dma_ch_samp_cos);
|
|
|
|
|
dma_channel_abort(dma_ch_samp_sin);
|
|
|
|
|
dma_channel_abort(dma_ch_samp_trig);
|
|
|
|
|
dma_channel_clear_chain_to(dma_ch_nco1);
|
|
|
|
|
dma_channel_clear_chain_to(dma_ch_nco2);
|
|
|
|
|
dma_channel_clear_chain_to(dma_ch_nco3);
|
|
|
|
|
dma_channel_clear_chain_to(dma_ch_nco4);
|
|
|
|
|
dma_channel_clear_chain_to(dma_ch_mix);
|
|
|
|
|
|
|
|
|
|
dma_channel_cleanup(dma_ch_rx);
|
|
|
|
|
dma_channel_cleanup(dma_ch_cp);
|
|
|
|
|
dma_channel_cleanup(dma_ch_cos);
|
|
|
|
|
dma_channel_cleanup(dma_ch_sin);
|
|
|
|
|
dma_channel_cleanup(dma_ch_pio_cos);
|
|
|
|
|
dma_channel_cleanup(dma_ch_pio_sin);
|
|
|
|
|
dma_channel_cleanup(dma_ch_samp_cos);
|
|
|
|
|
dma_channel_cleanup(dma_ch_samp_sin);
|
|
|
|
|
dma_channel_cleanup(dma_ch_samp_trig);
|
|
|
|
|
dma_channel_abort(dma_ch_nco1);
|
|
|
|
|
dma_channel_abort(dma_ch_nco2);
|
|
|
|
|
dma_channel_abort(dma_ch_nco3);
|
|
|
|
|
dma_channel_abort(dma_ch_nco4);
|
|
|
|
|
dma_channel_abort(dma_ch_mix);
|
|
|
|
|
|
|
|
|
|
dma_channel_unclaim(dma_ch_rx);
|
|
|
|
|
dma_channel_unclaim(dma_ch_cp);
|
|
|
|
|
dma_channel_unclaim(dma_ch_cos);
|
|
|
|
|
dma_channel_unclaim(dma_ch_sin);
|
|
|
|
|
dma_channel_unclaim(dma_ch_pio_cos);
|
|
|
|
|
dma_channel_unclaim(dma_ch_pio_sin);
|
|
|
|
|
dma_channel_unclaim(dma_ch_samp_cos);
|
|
|
|
|
dma_channel_unclaim(dma_ch_samp_sin);
|
|
|
|
|
dma_channel_unclaim(dma_ch_samp_trig);
|
|
|
|
|
dma_channel_cleanup(dma_ch_nco1);
|
|
|
|
|
dma_channel_cleanup(dma_ch_nco2);
|
|
|
|
|
dma_channel_cleanup(dma_ch_nco3);
|
|
|
|
|
dma_channel_cleanup(dma_ch_nco4);
|
|
|
|
|
dma_channel_cleanup(dma_ch_mix);
|
|
|
|
|
|
|
|
|
|
dma_timer_unclaim(dma_t_samp);
|
|
|
|
|
dma_channel_unclaim(dma_ch_nco1);
|
|
|
|
|
dma_channel_unclaim(dma_ch_nco2);
|
|
|
|
|
dma_channel_unclaim(dma_ch_nco3);
|
|
|
|
|
dma_channel_unclaim(dma_ch_nco4);
|
|
|
|
|
dma_channel_unclaim(dma_ch_mix);
|
|
|
|
|
|
|
|
|
|
dma_ch_rx = -1;
|
|
|
|
|
dma_ch_cp = -1;
|
|
|
|
|
dma_ch_cos = -1;
|
|
|
|
|
dma_ch_sin = -1;
|
|
|
|
|
dma_ch_pio_cos = -1;
|
|
|
|
|
dma_ch_pio_sin = -1;
|
|
|
|
|
dma_ch_samp_cos = -1;
|
|
|
|
|
dma_ch_samp_sin = -1;
|
|
|
|
|
dma_ch_samp_trig = -1;
|
|
|
|
|
dma_ch_nco1 = -1;
|
|
|
|
|
dma_ch_nco2 = -1;
|
|
|
|
|
dma_ch_nco3 = -1;
|
|
|
|
|
dma_ch_nco4 = -1;
|
|
|
|
|
dma_ch_mix = -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dma_t_samp = -1;
|
|
|
|
|
struct IQ {
|
|
|
|
|
int I, Q;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
inline static int nextQ(void)
|
|
|
|
|
{
|
|
|
|
|
static int x4, x3, x2, x1;
|
|
|
|
|
|
|
|
|
|
int x0 = gain * adc_fifo_get_blocking();
|
|
|
|
|
|
|
|
|
|
int x = x2 + x2 - x4 - x0;
|
|
|
|
|
x4 = x3;
|
|
|
|
|
x3 = x2;
|
|
|
|
|
x2 = x1;
|
|
|
|
|
x1 = x0;
|
|
|
|
|
|
|
|
|
|
return x;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
inline static struct IQ next_sample()
|
|
|
|
|
{
|
|
|
|
|
int I = 0, Q = 0;
|
|
|
|
|
|
|
|
|
|
I += nextQ();
|
|
|
|
|
Q += nextQ();
|
|
|
|
|
I -= nextQ();
|
|
|
|
|
Q -= nextQ();
|
|
|
|
|
|
|
|
|
|
static int dcI, dcQ;
|
|
|
|
|
|
|
|
|
|
I = ((I << 12) - dcI) >> 12;
|
|
|
|
|
dcI += I;
|
|
|
|
|
|
|
|
|
|
Q = ((Q << 12) - dcQ) >> 12;
|
|
|
|
|
dcQ += Q;
|
|
|
|
|
|
|
|
|
|
I += 127.4 * 512;
|
|
|
|
|
I /= 512;
|
|
|
|
|
|
|
|
|
|
Q += 127.4 * 512;
|
|
|
|
|
Q /= 512;
|
|
|
|
|
|
|
|
|
|
return (struct IQ){ I, Q };
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rf_rx(void)
|
|
|
|
|
{
|
|
|
|
|
const uint32_t base = (uint32_t)rx_cos;
|
|
|
|
|
int pos = 0;
|
|
|
|
|
|
|
|
|
|
while (true) {
|
|
|
|
|
if (multicore_fifo_rvalid()) {
|
|
|
|
|
multicore_fifo_pop_blocking();
|
|
|
|
|
@ -488,111 +325,32 @@ static void rf_rx(void)
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int head = (dma_hw->ch[dma_ch_in_cos].write_addr - base) / 4;
|
|
|
|
|
int delta = (head < pos ? head + RX_WORDS : head) - pos;
|
|
|
|
|
|
|
|
|
|
while (delta < RX_STRIDE) {
|
|
|
|
|
sleep_us(1);
|
|
|
|
|
head = (dma_hw->ch[dma_ch_in_cos].write_addr - base) / 4;
|
|
|
|
|
delta = (head < pos ? head + RX_WORDS : head) - pos;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const uint32_t *cos_ptr = rx_cos + pos;
|
|
|
|
|
const uint32_t *sin_ptr = rx_sin + pos;
|
|
|
|
|
|
|
|
|
|
pos = (pos + RX_STRIDE) & (RX_WORDS - 1);
|
|
|
|
|
|
|
|
|
|
uint8_t *block = iq_queue_buffer[iq_queue_pos];
|
|
|
|
|
uint8_t *blockptr = block;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Since every 2 samples add to either +1 or -1,
|
|
|
|
|
* the maximum amplitude in one direction is 1/2.
|
|
|
|
|
*/
|
|
|
|
|
int64_t max_amplitude = CLK_SYS_HZ / 2;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Since the waveform is normally half of the time
|
|
|
|
|
* above zero, we can halve once more.
|
|
|
|
|
*
|
|
|
|
|
* This is not perfect, so we do not max out the base
|
|
|
|
|
* gain but keep it slightly below the maximum to make
|
|
|
|
|
* sure we do not overshoot often.
|
|
|
|
|
*/
|
|
|
|
|
max_amplitude /= 2;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We are allowing the counters to only go as high
|
|
|
|
|
* as sampling rate.
|
|
|
|
|
*/
|
|
|
|
|
max_amplitude /= sample_rate;
|
|
|
|
|
|
|
|
|
|
for (int i = 0; i < IQ_SAMPLES; i++) {
|
|
|
|
|
int sI = 0, sQ = 0;
|
|
|
|
|
struct IQ IQ = next_sample();
|
|
|
|
|
int64_t I = IQ.I;
|
|
|
|
|
int64_t Q = IQ.Q;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* I: +I1 -I3 +Q2 -Q4
|
|
|
|
|
* Q: +Q1 -Q3 -I2 +I4
|
|
|
|
|
*/
|
|
|
|
|
sI += *cos_ptr++;
|
|
|
|
|
sI -= *cos_ptr++;
|
|
|
|
|
if (I < 0)
|
|
|
|
|
I = 0;
|
|
|
|
|
else if (I > 255)
|
|
|
|
|
I = 255;
|
|
|
|
|
|
|
|
|
|
sQ -= *cos_ptr++;
|
|
|
|
|
sQ += *cos_ptr++;
|
|
|
|
|
*blockptr++ = I;
|
|
|
|
|
|
|
|
|
|
sI -= *cos_ptr++;
|
|
|
|
|
sI += *cos_ptr++;
|
|
|
|
|
if (Q < 0)
|
|
|
|
|
Q = 0;
|
|
|
|
|
else if (Q > 255)
|
|
|
|
|
Q = 255;
|
|
|
|
|
|
|
|
|
|
sQ += *cos_ptr++;
|
|
|
|
|
sQ -= *cos_ptr++;
|
|
|
|
|
|
|
|
|
|
sQ += *sin_ptr++;
|
|
|
|
|
sQ -= *sin_ptr++;
|
|
|
|
|
|
|
|
|
|
sI += *sin_ptr++;
|
|
|
|
|
sI -= *sin_ptr++;
|
|
|
|
|
|
|
|
|
|
sQ -= *sin_ptr++;
|
|
|
|
|
sQ += *sin_ptr++;
|
|
|
|
|
|
|
|
|
|
sI -= *sin_ptr++;
|
|
|
|
|
sI += *sin_ptr++;
|
|
|
|
|
|
|
|
|
|
int64_t I = sI;
|
|
|
|
|
int64_t Q = sQ;
|
|
|
|
|
|
|
|
|
|
I *= 127;
|
|
|
|
|
I -= (max_amplitude * 181) / 256;
|
|
|
|
|
I /= max_amplitude;
|
|
|
|
|
|
|
|
|
|
if (I > 127)
|
|
|
|
|
I = 127;
|
|
|
|
|
else if (I < -128)
|
|
|
|
|
I = -128;
|
|
|
|
|
|
|
|
|
|
*blockptr++ = (uint8_t)I + 128;
|
|
|
|
|
|
|
|
|
|
Q *= 127;
|
|
|
|
|
Q -= (max_amplitude * 181) / 256;
|
|
|
|
|
Q /= max_amplitude;
|
|
|
|
|
|
|
|
|
|
if (Q > 127)
|
|
|
|
|
Q = 127;
|
|
|
|
|
else if (Q < -128)
|
|
|
|
|
Q = -128;
|
|
|
|
|
|
|
|
|
|
*blockptr++ = (uint8_t)Q + 128;
|
|
|
|
|
*blockptr++ = Q;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (queue_try_add(&iq_queue, &block)) {
|
|
|
|
|
iq_queue_pos = (iq_queue_pos + 1) & (IQ_QUEUE_LEN - 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Randomize LO phase in the next word. */
|
|
|
|
|
for (int i = 0; i < 8; i++) {
|
|
|
|
|
lo_tweak(lo_cos, COS_PHASE);
|
|
|
|
|
lo_tweak(lo_sin, SIN_PHASE);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
@ -600,18 +358,25 @@ static void run_command(uint8_t cmd, uint32_t arg)
|
|
|
|
|
{
|
|
|
|
|
if (0x01 == cmd) {
|
|
|
|
|
/* Tune to a new center frequency */
|
|
|
|
|
rx_lo_init(arg - sample_rate, true);
|
|
|
|
|
frequency = arg;
|
|
|
|
|
rx_lo_init(frequency + sample_rate);
|
|
|
|
|
} else if (0x02 == cmd) {
|
|
|
|
|
/* Set the rate at which IQ sample pairs are sent */
|
|
|
|
|
if (arg > (ADC_RATE / DECIMATE))
|
|
|
|
|
arg = ADC_RATE / DECIMATE;
|
|
|
|
|
|
|
|
|
|
sample_rate = arg;
|
|
|
|
|
dma_timer_set_fraction(dma_t_samp, 1, CLK_SYS_HZ / (sample_rate * DECIMATE));
|
|
|
|
|
rx_lo_init(arg - sample_rate, true);
|
|
|
|
|
adc_set_clkdiv(96.0f * ((float)ADC_RATE / (sample_rate * DECIMATE)) - 1.0f);
|
|
|
|
|
} else if (0x04 == cmd) {
|
|
|
|
|
/* Set the tuner gain level */
|
|
|
|
|
bias_set_gain((arg + 14) / 30);
|
|
|
|
|
gain = INIT_GAIN * powf(10.0f, arg / 200.0f);
|
|
|
|
|
} else if (0x0d == cmd) {
|
|
|
|
|
/* Set tuner gain by the tuner's gain index */
|
|
|
|
|
bias_set_gain((gains[arg] + 14) / 30);
|
|
|
|
|
|
|
|
|
|
if (arg >= NUM_GAINS)
|
|
|
|
|
arg = NUM_GAINS - 1;
|
|
|
|
|
|
|
|
|
|
gain = INIT_GAIN * powf(10.0f, gains[arg] / 200.0f);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
@ -639,34 +404,11 @@ static int check_command(void)
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void do_rx(int rx_pin, int bias_pin)
|
|
|
|
|
static void do_rx()
|
|
|
|
|
{
|
|
|
|
|
rf_rx_start(rx_pin, bias_pin);
|
|
|
|
|
rf_rx_start();
|
|
|
|
|
sleep_us(100);
|
|
|
|
|
|
|
|
|
|
dma_ch_in_cos = dma_claim_unused_channel(true);
|
|
|
|
|
dma_ch_in_sin = dma_claim_unused_channel(true);
|
|
|
|
|
|
|
|
|
|
dma_channel_config dma_conf;
|
|
|
|
|
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_in_cos);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, true);
|
|
|
|
|
channel_config_set_ring(&dma_conf, true, RX_BITS_DEPTH);
|
|
|
|
|
channel_config_set_dreq(&dma_conf, pio_get_dreq(pio1, 2, false));
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_in_sin);
|
|
|
|
|
dma_channel_configure(dma_ch_in_cos, &dma_conf, rx_cos, &pio1->rxf[2], 2, false);
|
|
|
|
|
|
|
|
|
|
dma_conf = dma_channel_get_default_config(dma_ch_in_sin);
|
|
|
|
|
channel_config_set_transfer_data_size(&dma_conf, DMA_SIZE_32);
|
|
|
|
|
channel_config_set_read_increment(&dma_conf, false);
|
|
|
|
|
channel_config_set_write_increment(&dma_conf, true);
|
|
|
|
|
channel_config_set_ring(&dma_conf, true, RX_BITS_DEPTH);
|
|
|
|
|
channel_config_set_dreq(&dma_conf, pio_get_dreq(pio1, 3, false));
|
|
|
|
|
channel_config_set_chain_to(&dma_conf, dma_ch_in_cos);
|
|
|
|
|
dma_channel_configure(dma_ch_in_sin, &dma_conf, rx_sin, &pio1->rxf[3], 2, true);
|
|
|
|
|
|
|
|
|
|
multicore_launch_core1(rf_rx);
|
|
|
|
|
|
|
|
|
|
const uint8_t *block;
|
|
|
|
|
@ -684,6 +426,11 @@ static void do_rx(int rx_pin, int bias_pin)
|
|
|
|
|
if (queue_try_remove(&iq_queue, &block)) {
|
|
|
|
|
fwrite(block, IQ_BLOCK_LEN, 1, stdout);
|
|
|
|
|
fflush(stdout);
|
|
|
|
|
} else {
|
|
|
|
|
int wait = rnd_next() & 0x1fff;
|
|
|
|
|
|
|
|
|
|
for (int i = 0; i < wait; i++)
|
|
|
|
|
asm volatile("nop");
|
|
|
|
|
}
|
|
|
|
|
}
|
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@ -694,21 +441,24 @@ done:
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multicore_reset_core1();
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rf_rx_stop();
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dma_channel_abort(dma_ch_in_cos);
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dma_channel_abort(dma_ch_in_sin);
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dma_channel_cleanup(dma_ch_in_cos);
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dma_channel_cleanup(dma_ch_in_sin);
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dma_channel_unclaim(dma_ch_in_cos);
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dma_channel_unclaim(dma_ch_in_sin);
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dma_ch_in_cos = -1;
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dma_ch_in_sin = -1;
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}
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int main()
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{
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vreg_set_voltage(VREG_VOLTAGE);
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/* Step the USB PLL up to 192 MHz and overclock ADC with it. */
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pll_init(pll_usb, 1, 1536 * MHZ, 4, 2);
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clock_configure(clk_usb, 0, CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
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4 * USB_CLK_KHZ * KHZ, USB_CLK_KHZ * KHZ);
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clock_configure(clk_adc, 0, CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
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4 * USB_CLK_KHZ * KHZ, 4 * USB_CLK_KHZ * KHZ);
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/* Adjust system clock as well. */
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set_sys_clock_khz(CLK_SYS_HZ / KHZ, true);
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clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, CLK_SYS_HZ,
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CLK_SYS_HZ);
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@ -724,7 +474,16 @@ int main()
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queue_init(&iq_queue, sizeof(uint8_t *), IQ_QUEUE_LEN);
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rx_lo_init(INIT_FREQ - INIT_SAMPLE_RATE, true);
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/* Init ADC */
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adc_init();
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gpio_disable_pulls(RX_PIN);
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adc_gpio_init(RX_PIN);
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adc_select_input(RX_PIN - 26);
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adc_fifo_setup(true, true, 1, false, false);
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adc_set_clkdiv(96.0f * ((float)ADC_RATE / (sample_rate * DECIMATE)) - 1.0f);
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adc_run(true);
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rx_lo_init(frequency + sample_rate);
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while (true) {
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if (check_command() > 0) {
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@ -734,7 +493,7 @@ int main()
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fwrite(header, sizeof header, 1, stdout);
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fflush(stdout);
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do_rx(10, 11);
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do_rx();
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}
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sleep_ms(10);
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